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mb91f467ba/466ba mb91f465bb/464bb fr60 mb91460b series, 32-bit microcontroller datasheet cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04608 rev. *a revised april 25, 2016 mb91460b series is a line of general-purpose 32-bit risc micr ocontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer device s and on-board vehicle systems. this series uses the fr60 cpu, which is compatible with the fr family of cpus. this series contains the lin-usart and can controllers. note: mb91f466ba, mb91f464bb - these devices are under development. features fr60 cpu core 32-bit risc, load/store architecture, five-stage pipeline 16-bit fixed-length instruct ions (basic instructions) instruction execution speed: 1 instruction per cycle instructions including memory-t o-memory transfer, bit manip- ulation, and barrel shift instructions: instructions suitable for embedded applications function entry/exit instructions and register data multi-load store instructions: instru ctions supporting c language register interlock function: facilitating assembly-language coding built-in multiplier with in struction-level support signed 32-bit multiplication: 5 cycles signed 16-bit multiplication: 3 cycles interrupts (save pc/ps): 6 cycles (16 priority levels) harvard architecture enabling program access and data access to be performed simultaneously instructions compatible with the fr family internal peripheral resources general-purpose ports: maximum 108 ports dmac (dma controller) maximum of 5 channels able to operate simultaneously 2 transfer sources (internal peripheral/software) activation source can be selected using software addressing mode specifies full 32-bit addresses (increment/decrement/fixed) transfer mode (demand tran sfer/burst transfer/step transfer/block transfer) transfer data size selectable from 8/16/32-bit multi-byte transfer enabled (by software) dmac descriptor in i/o areas (200 h to 240 h , 1000 h to 1024 h ) a/d converter (successive approximation type) 10-bit resolution: maximum 32 channels conversion time: minimum 1 ? s external interrupt inputs: maximum 16 channels 6 channels shared with can rx or i 2 c pins bit search module (for realos) function to search the first bit position of ??1??, ??0??, ??changed?? from the msb (most significant bit) within one word lin-usart (full duplex double buffer): 4 or 7 channels, depending on pin multiplexing clock synchronous/asynchronous selectable sync-break detection internal dedicated baud rate generator i 2 c bus interface (supports 400 kbps): 2 channels master/slave transmission and reception arbitration function, cloc k synchronization function can controller (c-can): 3 or 6 channels (depending on the device) maximum transfer speed: 1 mbps 32 transmission/reception message buffers sound generator: 1 channel tone frequency : pwm frequency divide-by-two (reload value ? 1) alarm comparator: 1 channel monitor external voltage generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) 16-bit ppg timer: maximum 16 channels 16-bit reload timer: 8 channels 16-bit free-run timer: 8 channels (1 channel each for icu and ocu) input capture: maximum 8 chan nels (operates in conjunction with the free-run timer) output compare: maximum 8 channels (operates in conjunction with the free-run timer) up/down counter: 2 channels (2*8-bit or 1*16-bit) watchdog timer real-time clock low-power consumption modes : sleep/stop mode function low voltage detection circuit clock supervisor monitors the sub-clock (32 khz) and the main clock (4 mhz) ,
mb91460b series document number: 002-04608 rev. *a page 2 of 126 and switches to a recovery clock (cr oscillator, etc.) when the oscillations stop. clock modulator clock monitor sub-clock calibration corrects the real-time clock time r when operating with the 32 khz or cr oscillator main oscillator stabilization timer generates an interrupt in sub-cl ock mode after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter sub-oscillator stabilization timer generates an interrupt in main clock mode after the stabili- zation wait time has elapsed on the 15-bit stabilization wait time counter package and technology package: qfp-144 cmos 180 nm technology power supply range 3 v to 5 v (1.8 v internal logic provided by a step-down voltage converter) operating temperature range: between ? 40c and ? 125c
mb91460b series document number: 002-04608 rev. *a page 3 of 126 contents 1. product lineup ............................................................. 4 2. pin assignment ............................................................ 7 2.1 mb91f467ba/466ba with md_3=1............................... 7 2.2 mb91f467ba/466ba with md_3=0............................... 8 2.3 mb91f465bb/464bb with md_3=1............................... 9 2.4 mb91f465bb/464bb with md_3=0............................. 10 3. pin description ........................................................... 11 3.1 mb91f467ba/466ba a nd mb91f465bb/464bb with md_3=1 ....................................................................... 11 3.2 mb91f467ba/466ba a nd mb91f465bb/464bb with md_3=0 ....................................................................... 16 4. i/o circuit types ......................................................... 21 5. handling devices ....................................................... 27 5.1 preventing latch-up..................................................... 27 5.2 handling of unused input pins .............. .............. .......... 27 5.3 power supply pins........................................................ 27 5.4 crystal oscillator circuit ..... ........................................... 27 5.5 notes on using external cloc k ...................................... 27 5.6 mode pins (md_x)........................................................ 28 5.7 notes on operating in pll clock mode ........................ 28 5.8 pull-up control .............................................................. 28 6. notes on debugger .................................................... 29 6.1 execution of the reti command ................................ 29 6.2 break function .............................................................. 29 6.3 operand break ............................................................. 29 6.4 notes on ps register.................................................... 29 7. block diagram ............................................................ 30 7.1 mb91f467ba/466ba with md_3=1............................. 30 7.2 mb91f467ba/466ba with md_3=0............................. 31 7.3 mb91f465bb/464bb with md_3=1............................. 32 7.4 mb91f465bb/464bb with md_3=0............................. 33 8. cpu and control unit ................................................ 34 8.1 features....................................................................... 34 8.2 internal architecture..................................................... 34 8.3 programming model..................................................... 35 8.4 registers...................................................................... 36 9. embedded program/data memory (flash) .............. 39 9.1 flash features .............................................................. 39 9.2 operation modes ......................................................... 39 9.3 flash access in cpu mode ......................................... 40 9.4 parallel flash programming mode............................... 47 9.5 poweron sequence in parallel programming mode .... 50 9.6 flash security .............................................................. 50 10. memory space ............................................................ 53 11. memory maps ............................................................. 54 11.1 mb91f467ba, mb91f466ba ...................................... 54 11.2 mb91f465bb, mb91f464bb ...................................... 55 12. i/o map ........................................................................ 56 12.1 mb91f467ba/466ba, mb91 f465bb/464bb............... 56 12.2 flash memory and external bus area .......................... 83 13. interrupt vector table ................................................. 87 14. recommended settings ............................................. 91 14.1 pll and clock gear settings.. ............... .............. ......... 91 14.2 clock modulator settings....... ........................................ 92 15. electrical characteristics ........................................... 97 15.1 absolute maximum ratings .......................................... 97 15.2 recommended operating conditi ons......................... 100 15.3 dc characteristics ................ ...................................... 101 15.4 a/d converter characteristic s .................................... 104 15.5 alarm comparator characterist ics.............................. 108 15.6 flash memory program/erase characteristics ........... 109 15.7 ac characteristics ................ ...................................... 110 16. ordering information ................................................ 122 17. package dimension .................................................. 123 18. revision history ........................................................ 124 19. main changes in this edition ................................... 124 document history .............................................................. 125
mb91460b series document number: 002-04608 rev. *a page 4 of 126 1. product lineup feature mb91v460 mb91f465bb/464bb mb91f467ba/466ba max. core frequency (clkb) 80 mhz 100 mhz 96 mhz max. resource frequency (clkp) 40 mhz 50 mhz 48 mhz max. external bus frequency (clkt) 40 mhz 50 mhz 48 mhz max. can frequency (clkcan) 20 mhz 50 mhz 48 mhz technology 0.35 ? m0.18 ? m0.18 ? m watchdog yes yes yes watchdog (rc osc. based) yes (disengageable) yes yes bit search yes yes yes reset input (initx) yes yes yes hardware standby input (hstx) yes no no clock modulator yes yes yes clock monitor yes yes yes low power mode yes yes yes dma 5 ch 5 ch 5 ch mmu/mpu mpu (16 ch) [1] mpu (8 ch) [1] mpu (8 ch) [1] flash memory emulation sram 32bit read data mb91f465bb: 544 kbyte mb91f464bb: 416 kbyte mb91f467ba: 1088 kbyte mb91f466ba: 832 kbyte satellite flash memory - - - flash protection - yes yes d-ram 64 kbyte 24 kbyte 24 kbyte id-ram 64 kbyte 16 kbyte 16 kbyte flash-cache (instruction cache) 16 kbyte 8 kbyte 8 kbyte boot-rom / bi-rom 4 kbyte fixed 4 kbyte 4 kbyte rtc 1 ch 1 ch 1 ch free running timer 8 ch 8 ch [2] 8 ch [2] icu 8 ch md_3=0: 8 ch md_3=1: 4 ch [3] md_3=0: 8 ch md_3=1: 4 ch [3] ocu 8 ch md_3=0: 8 ch md_3=1: 4 ch [4] md_3=0: 8 ch md_3=1: 4 ch [4] reload timer 8 ch 8 ch [5] 8 ch [5] ppg 16-bit 16 ch md_3=0: 16 ch md_3=1: 8 ch [6] md_3=0: 16 ch md_3=1: 8 ch [6] pfm 16-bit 1 ch - - sound generator 1 ch 1 ch 1 ch up/down counter (8/16 bit) 4 ch (8-bit) / 2 ch (16-bit) md_3=0: 2 ch (8-bit) / 1 ch (16bit) md_3=1: na [7] md_3=0: 2 ch (8-bit) / 1 ch (16bit) md_3=1: na [7] c_can 6 ch (128msg) 3 ch (32msg) 6 ch (32msg)
mb91460b series document number: 002-04608 rev. *a page 5 of 126 1. mpu channels use edsu breakpoint registers (shared operation between mpu and edsu). 2. free running timer: md3=0 : ch 1 and 0 cannot select external clock (bit7 of tccs1,0) md3=1: ch 3, 2, 1, and 0 cannot select external clock (bit7 of tccs3,2,1,0) feature mb91v460 mb91f465bb/464bb mb91f467ba/466ba lin-usart 4 ch + 4 ch fifo + 8 ch md_3=0: 3 ch + 4 ch fifo [8] md_3=1: 4 ch fifo md_3=0: 3 ch + 4 ch fifo [8] md_3=1: 4 ch fifo i 2 c (400k) 4 ch 2 ch 2 ch fr external bus yes (32bit addr, 32bit data) md_3=0: no md_3=1: yes (22bit addr, 16bit data) md_3=0: no md_3=1: yes (22bit addr, 16bit data) external interrupts 16 ch md_3=0: 16 ch md_3=1: 12 ch [9] md_3=0: 16 ch md_3=1: 12 ch [9] nmi interrupts 1 ch 1 ch 1 ch smc 6 ch - - lcd controller (40x4) 1 ch - - adc (10-bit) 32 ch md_3=0: 32 ch md_3=1: 16 ch md_3=0: 32 ch md_3=1: 16 ch alarm comparator 2 ch 1 ch 1 ch supply supervisor (low voltage detection) yes yes yes clock supervisor yes yes yes main clock oscillator 4 mhz 4 mhz 4 mhz sub clock oscillator 32khz 32khz 32khz rc oscillator 100khz 100khz / 2mhz 100khz / 2mhz pll x 20 x 25 x 25 dsu4 yes no no edsu yes (32 bp) [1] yes (16 bp) [1] yes (16 bp) [1] supply voltage 3v/5v 3v/5v 3v/5v regulator yes yes yes power consumption n.a. < 1.3 w < 1.3 w temperature range (ta) 0..70 c -40..125 c -40..125 c package bga-660 qfp-144 qfp-144 power on to pll run < 20 ms < 20 ms < 20 ms flash download time n.a. < 5 sec. typical < 6 sec. typical
mb91460b series document number: 002-04608 rev. *a page 6 of 126 3. icu: md3=1: do not set pfr = 1 & epfr = 1 (for lin synch field detect). 4. ocu: md3=1: you cannot use external out-port (but, ocu-function is active.) 5. reload timer: md3=1: ch 7, 6, 5, and 4 cannot select external event 6. ppg: md3=1: you can use ch15 to 8 of ppg . ch15 to12 cannot select external trigger. 7. up/down counter: md3=1: you can use timer-mode only. 8. lin-usart ch 0 (shared with external bus) can be used for asynchronous mode only. 9. external interrupts: int7 to int4(shared with external bus) can be used for md3=0 mode only. int0 (shared with external bus) can be used for md3=0 mode only.
mb91460b series document number: 002-04608 rev. *a page 7 of 126 2. pin assignment 2.1 mb91f467ba/466ba with md_3=1 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vdd5 avcc5 avrh5 avss5 alarm_0 p18_6/ sck7/ ck 7 p18_5/ sot7 p18_4/ sin7 p18_2/ sck6/ ck 6 p18_1/ sot6 p18_0/ sin6 p19_6/ sck5/ ck 5 p19_5/ sot5 p19_4/ sin5 p19_2/ sck4/ ck 4 p19_1/ sot4 p19_0/ sin4 vss5 vdd5 vdd5r vdd5r vcc18c vss5 nmix initx x1a x0a vss5 x0 x1 md_3 monclk md_2 md_1 md_0 vss5 vss5 p07_6/ a6 p07_7/ a7 p06_0/ a8 p06_1/ a9 p 06_2/ a10 p 06_3/ a11 p 06_4/ a12 p 06_5/ a13 p 06_6/ a14 p 06_7/ a15 p 05_0/ a16 p 05_1/ a17 p 05_2/ a18 p 05_3/ a19 p 05_4/ a20 p 05_5/ a21 vdd35 vss5 p 01_0/ d16 p 01_1/ d17 p 01_2/ d18 p 01_3/ d19 p 01_4/ d20 p 01_5/ d21 p 01_6/ d22 p 01_7/ d23 p 00_0/ d24 p 00_1/ d25 p 00_2/ d26 p 00_3/ d27 p 00_4/ d28 p 00_5/ d29 p 00_6/ d30 p 00_7/ d31 vdd35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vdd35 p07_5/ a5 p07_4/ a4 p07_3/ a3 p07_2/ a2 p07_1/ a1 p07_0/ a0 p15_3/ ocu3/ tot3 p15_2/ ocu2/ tot2 p15_1/ ocu1/ tot1 p15_0/ ocu0/ tot0 p14_3/ icu3/ tin3/ ttg3/ 1 1 p14_2/ icu2/ tin2/ ttg2/ 1 0 p14_1/ icu1/ tin1/ ttg1/ 9 p14_0/ icu0/ tin0/ ttg0/ 8 p24_3/ int3 p24_2/ int2 vss5 vdd5 p28_7/ an15 p28_6/ an14 p28_5/ an13 p28_4/ an12 p28_3/ an11 p28_2/ an10 p28_1/ an9 p28_0/ an8 p29_7/ an7 p29_6/ an6 p29_5/ an5 p29_4/ an4 p29_3/ an3 p29_2/ an2 p29_1/ an1 p29_0/ an0 vss5 vss5 p10_0/ sysclk p09_0/ csx0 p09_1/ csx1 p08_0/ wrx0 p08_4/ rdx p08_7/ rdy wrx1 p24_1/ int1 p23_0/ rx0/ int8 p23_1/ tx0 p23_2/ rx1/ int9 p23_3/ tx1 p23_4/ rx2/ int10 p23_5/ tx2 p23_6/ rx3/ int11 p23_7/ tx3 vdd5 vss5 p22_0/ rx4/ int12 p22_1/ tx4 p22_2/ rx5/ int13 p22_3/ tx5 p22_4/ sda0/ int14 p22_5/ scl0 p22_6/ sda1/ int15 p22_7/ scl1 p16_0/ ppg8 p16_1/ ppg9 p16_2/ ppg10 p16_3/ ppg11 p16_4/ ppg12/ sga p16_5/ ppg13/ sgo p16_6/ ppg14 p 16_7/ ppg15/ atgx vdd5 lqfp-144
mb91460b series document number: 002-04608 rev. *a page 8 of 126 2.2 mb91f467ba/466ba with md_3=0 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vdd5 avcc5 avrh5 avss5 alarm_0 p18_6/ sck7/ ck7 p18_5/ sot7 p18_4/ sin7 p18_2/ sck6/ ck6 p18_1/ sot6 p18_0/ sin6 p19_6/ sck5/ ck5 p19_5/ sot5 p19_4/ sin5 p19_2/ sck4/ ck4 p19_1/ sot4 p19_0/ sin4 vss5 vdd5 vdd5r vdd5r vcc18c vss5 nmix initx x1a x0a vss5 x0 x1 md_3 monclk md_2 md_1 md_0 vss5 vss5 p27_6/ an22 p27_7/ an23 p26_0/ an24 p26_1/ an25 p26_2/ an26 p26_3/ an27 p26_4/ an28 p26_5/ an29 p26_6/ an30 p26_7/ an31 p24_4/ int4 p24_5/ int5 p24_6/ int6 p24_7/ int7 p21_0/ sin0 p21_1/ sot0 vdd35 vss5 p14_4/ icu4/ tin4/ ttg12/ 4 p14_5/ icu5/ tin5/ ttg13/ 5 p14_6/ icu6/ tin6/ ttg14/ 6 p14_7/ icu7/ tin7/ ttg15/ 7 p15_4/ ocu4/ tot4 p15_5/ ocu5/ tot5 p15_6/ ocu6/ tot6 p15_7/ ocu7/ tot7 p17_0/ ppg0 p17_1/ ppg1 p17_2/ ppg2 p17_3/ ppg3 p17_4/ ppg4 p17_5/ ppg5 p17_6/ ppg6 p17_7/ ppg7 vdd35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vdd35 p27_5/ an21 p27_4/ an20 p27_3/ an19 p27_2/ an18 p27_1/ an17 p27_0/ an16 p15_3/ ocu3/ tot3 p15_2/ ocu2/ tot2 p15_1/ ocu1/ tot1 p15_0/ ocu0/ tot0 p14_3/ icu3/ tin3/ ttg3/ 11 p14_2/ icu2/ tin2/ ttg2/ 10 p14_1/ icu1/ tin1/ ttg1/ 9 p14_0/ icu0/ tin0/ ttg0/ 8 p24_3/ int3 p24_2/ int2 vss5 vdd5 p28_7/ an15 p28_6/ an14 p28_5/ an13 p28_4/ an12 p28_3/ an11 p28_2/ an10 p28_1/ an9 p28_0/ an8 p29_7/ an7 p29_6/ an6 p29_5/ an5 p29_4/ an4 p29_3/ an3 p29_2/ an2 p29_1/ an1 p29_0/ an0 vss5 vss5 p20_0/sin2/ain0 p20_1/sot2/bin0 p20_2/sck2/zin0/ck2 p20_4/sin3/ain1 p20_5/sot3/bin1 p20_6/sck3/zin1/ck3 p24_0/int0 p24_1/int1 p23_0/rx0/int8 p23_1/tx0 p23_2/rx1/int9 p23_3/tx1 p23_4/rx2/int10 p23_5/tx2 p23_6/rx3/int11 p23_7/tx3 vdd5 vss5 p22_0/rx4/int12 p22_1/tx4 p22_2/rx5/int13 p22_3/tx5 p22_4/sda0/int14 p22_5/scl0 p22_6/sda1/int15 p22_7/scl1 p16_0/ppg8 p16_1/ppg9 p16_2/ppg10 p16_3/ppg11 p16_4/ppg12/sga p16_5/ppg13/sgo p16_6/ppg14 p16_7/ppg15/atgx vdd5 lqfp-144
mb91460b series document number: 002-04608 rev. *a page 9 of 126 2.3 mb91f465bb/464bb with md_3=1 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vdd5 avcc5 avrh5 avss5 alarm_0 p18_6/ sck7/ ck 7 p18_5/ sot7 p18_4/ sin7 p18_2/ sck6/ ck 6 p18_1/ sot6 p18_0/ sin6 p19_6/ sck5/ ck 5 p19_5/ sot5 p19_4/ sin5 p19_2/ sck4/ ck 4 p19_1/ sot4 p19_0/ sin4 vss5 vdd5 vdd5r vdd5r vcc18c vss5 nmix initx x1a x0a vss5 x0 x1 md_3 monclk md_2 md_1 md_0 vss5 vss5 p07_6/ a6 p07_7/ a7 p06_0/ a8 p06_1/ a9 p 06_2/ a10 p 06_3/ a11 p 06_4/ a12 p 06_5/ a13 p 06_6/ a14 p 06_7/ a15 p 05_0/ a16 p 05_1/ a17 p 05_2/ a18 p 05_3/ a19 p 05_4/ a20 p 05_5/ a21 vdd35 vss5 p 01_0/ d16 p 01_1/ d17 p 01_2/ d18 p 01_3/ d19 p 01_4/ d20 p 01_5/ d21 p 01_6/ d22 p 01_7/ d23 p 00_0/ d24 p 00_1/ d25 p 00_2/ d26 p 00_3/ d27 p 00_4/ d28 p 00_5/ d29 p 00_6/ d30 p 00_7/ d31 vdd35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vdd35 p07_5/ a5 p07_4/ a4 p07_3/ a3 p07_2/ a2 p07_1/ a1 p07_0/ a0 p15_3/ ocu3/ tot3 p15_2/ ocu2/ tot2 p15_1/ ocu1/ tot1 p15_0/ ocu0/ tot0 p14_3/ icu3/ tin3/ ttg3/ 1 1 p14_2/ icu2/ tin2/ ttg2/ 1 0 p14_1/ icu1/ tin1/ ttg1/ 9 p14_0/ icu0/ tin0/ ttg0/ 8 p24_3/ int3 p24_2/ int2 vss5 vdd5 p28_7/ an15 p28_6/ an14 p28_5/ an13 p28_4/ an12 p28_3/ an11 p28_2/ an10 p28_1/ an9 p28_0/ an8 p29_7/ an7 p29_6/ an6 p29_5/ an5 p29_4/ an4 p29_3/ an3 p29_2/ an2 p29_1/ an1 p29_0/ an0 vss5 vss5 p10_0/ sysclk p09_0/ csx0 p09_1/ csx1 p08_0/ wrx0 p08_4/ rdx p08_7/ rdy p08_1/ wrx1 p24_1/ int1 p23_0/ rx0/ int8 p23_1/ tx0 p23_2/ rx1/ int9 p23_3/ tx1 p23_4/ rx2/ int10 p23_5/ tx2 p23_6/ int11 p23_7 vdd5 vss5 p22_0/ int12 p22_1 p22_2/ int13 p22_3 p22_4/ sda0/ int14 p22_5/ scl0 p22_6/ sda1/ int15 p22_7/ scl1 p16_0/ ppg8 p16_1/ ppg9 p16_2/ ppg10 p16_3/ ppg11 p16_4/ ppg12/ sga p16_5/ ppg13/ sgo p16_6/ ppg14 p 16_7/ ppg15/ atgx vdd5 lqfp-144
mb91460b series document number: 002-04608 rev. *a page 10 of 126 2.4 mb91f465bb/464bb with md_3=0 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vdd5 avcc5 avrh5 avss5 alarm_0 p18_6/ sck7/ ck7 p18_5/ sot7 p18_4/ sin7 p18_2/ sck6/ ck6 p18_1/ sot6 p18_0/ sin6 p19_6/ sck5/ ck5 p19_5/ sot5 p19_4/ sin5 p19_2/ sck4/ ck4 p19_1/ sot4 p19_0/ sin4 vss5 vdd5 vdd5r vdd5r vcc18c vss5 nmix initx x1a x0a vss5 x0 x1 md_3 monclk md_2 md_1 md_0 vss5 vss5 p27_6/ an22 p27_7/ an23 p26_0/ an24 p26_1/ an25 p26_2/ an26 p26_3/ an27 p26_4/ an28 p26_5/ an29 p26_6/ an30 p26_7/ an31 p24_4/ int4 p24_5/ int5 p24_6/ int6 p24_7/ int7 p21_0/ sin0 p21_1/ sot0 vdd35 vss5 p14_4/ icu4/ tin4/ ttg12/ 4 p14_5/ icu5/ tin5/ ttg13/ 5 p14_6/ icu6/ tin6/ ttg14/ 6 p14_7/ icu7/ tin7/ ttg15/ 7 p15_4/ ocu4/ tot4 p15_5/ ocu5/ tot5 p15_6/ ocu6/ tot6 p15_7/ ocu7/ tot7 p17_0/ ppg0 p17_1/ ppg1 p17_2/ ppg2 p17_3/ ppg3 p17_4/ ppg4 p17_5/ ppg5 p17_6/ ppg6 p17_7/ ppg7 vdd35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vdd35 p27_5/ an21 p27_4/ an20 p27_3/ an19 p27_2/ an18 p27_1/ an17 p27_0/ an16 p15_3/ ocu3/ tot3 p15_2/ ocu2/ tot2 p15_1/ ocu1/ tot1 p15_0/ ocu0/ tot0 p14_3/ icu3/ tin3/ ttg3/ 11 p14_2/ icu2/ tin2/ ttg2/ 10 p14_1/ icu1/ tin1/ ttg1/ 9 p14_0/ icu0/ tin0/ ttg0/ 8 p24_3/ int3 p24_2/ int2 vss5 vdd5 p28_7/ an15 p28_6/ an14 p28_5/ an13 p28_4/ an12 p28_3/ an11 p28_2/ an10 p28_1/ an9 p28_0/ an8 p29_7/ an7 p29_6/ an6 p29_5/ an5 p29_4/ an4 p29_3/ an3 p29_2/ an2 p29_1/ an1 p29_0/ an0 vss5 vss5 p20_0/ sin2/ ain0 p20_1/ sot2/ bin0 p20_2/ sck2/ zin0/ ck2 p20_4/ sin3/ ain1 p20_5/ sot3/ bin1 p20_6/ sck3/ zin1/ ck3 p24_0/ int0 p24_1/ int1 p23_0/ rx0/ int8 p23_1/ tx0 p23_2/ rx1/ int9 p23_3/ tx1 p23_4/ rx2/ int10 p23_5/ tx2 p23_6/ int11 p23_7 vdd5 vss5 p22_0/ int12 p22_1 p22_2/ int13 p22_3 p22_4/ sda0/ int14 p22_5/ scl0 p22_6/ sda1/ int15 p22_7/ scl1 p16_0/ ppg8 p16_1/ ppg9 p16_2/ ppg10 p16_3/ ppg11 p16_4/ ppg12/ sga p16_5/ ppg13/ sgo p16_6/ ppg14 p16_7/ ppg15/ atgx vdd5 lqfp-144
mb91460b series document number: 002-04608 rev. *a page 11 of 126 3. pin description 3.1 mb91f467ba/466ba and mb91f465bb/464bb with md_3=1 pin no. pin name i/o i/o circuit type [1] function 2, 3 p07_6, p07_7 i/o b general-purpose input/output port a6, a7 signal pins of external address bus (bit6 to bit7) 4 to 11 p06_0 to p06_7 i/o b general-purpose input/output port a8 to a15 signal pins of external address bus (bit8 to bit15) 12 to 17 p05_0 to p05_5 i/o a general-purpose input/output port a16 to a21 signal pins of external address bus (bit16 to bit21) 20 to 27 p01_0 to p01_7 i/o a general-purpose input/output port d16 to d23 signal pins of external data bus (bit16 to bit23) 28 to 35 p00_0 to p00_7 i/o a general-purpose input/output port d24 to d31 signal pins of external data bus (bit24 to bit31) 38 p10_0 i/o a general-purpose input/output port sysclk external bus clock output pin 39 p09_0 i/o a general-purpose input/output port csx0 chip select output pins 40 p09_1 i/o a general-purpose input/output port csx1 chip select output pins 41 p08_0 i/o a general-purpose input/output port wrx0 external write strobe output pins 42 p08_4 i/o a general-purpose input/output port rdx external read strobe output pin 43 p08_7 i/o a general-purpose input/output port rdy external ready input pin 44 p08_1 not on mb91f467ba/mb91f466 ba i/o a general-purpose input/output port wrx1 external write strobe output pins int0 not on mb91f467ba/mb91f466 ba external interrupt input, can on ly be used in general-purpose io port mode 45 p24_1 i/o a general-purpose input/output port int1 external interrupt input pins 46 p23_0 i/o a general-purpose input/output port rx0 rx input pin of can0 int8 external interrupt input pins 47 p23_1 i/o a general-purpose input/output port tx0 tx output pin of can0
mb91460b series document number: 002-04608 rev. *a page 12 of 126 48 p23_2 i/o a general-purpose input/output port rx1 rx input pin of can1 int9 external interrupt input pins 49 p23_3 i/o a general-purpose input/output port tx1 tx output pin of can1 50 p23_4 i/o a general-purpose input/output port rx2 rx input pin of can2 int10 external interrupt input pin 51 p23_5 i/o a general-purpose input/output port tx2 tx output pin of can2 52 p23_6 i/o a general-purpose input/output port int11 external interrupt input pin mb91f467ba/mb91f466 ba: rx3 rx input pin of can3 53 p23_7 i/o a general-purpose input/output port mb91f467ba/mb91f466 ba: tx3 tx output pin of can3 56 p22_0 i/o a general-purpose input/output port int12 external interrupt input pin mb91f467ba/mb91f466 ba: rx4 rx input pin of can4 57 p22_1 i/o a general-purpose input/output port mb91f467ba/mb91f466 ba: tx4 tx output pin of can4 58 p22_2 i/o a general-purpose input/output port int13 external interrupt input pin mb91f467ba/mb91f466 ba: rx5 rx input pin of can5 59 p22_3 i/o a general-purpose input/output port mb91f467ba/mb91f466 ba: tx5 tx output pin of can5 60 p22_4 i/o c general-purpose input/output port sda0 i 2 c bus data input/output pin (open drain) int14 external interrupt input pin 61 p22_5 i/o c general-purpose input/output port scl0 i 2 c bus clock input/output pin (open drain) 62 p22_6 i/o c general-purpose input/output port sda1 i 2 c bus data input/output pin (open drain) int15 external interrupt input pin 63 p22_7 i/o c general-purpose input/output port scl1 i 2 c bus clock input/output pin (open drain) pin no. pin name i/o i/o circuit type [1] function
mb91460b series document number: 002-04608 rev. *a page 13 of 126 64 p16_0 i/o a general-purpose input/output port ppg8 output pins of ppg timer 65 p16_1 i/o a general-purpose input/output port ppg9 output pins of ppg timer 66 p16_2 i/o a general-purpose input/output port ppg10 output pins of ppg timer 67 p16_3 i/o a general-purpose input/output port ppg11 output pins of ppg timer 68 p16_4 i/o a general-purpose input/output port ppg12 output pins of ppg timer sga sga output pin of sound generator 69 p16_5 i/o a general-purpose input/output port ppg13 output pins of ppg timer sgo sg0 output pin of sound generator 70 p16_6 i/o a general-purpose input/output port ppg14 output pins of ppg timer 71 p16_7 i/o a general-purpose input/output port ppg15 output pins of ppg timer atgx a/d converter external trigger input pin 74 to 76 md_0 to md_2 i g mode setting pins 77 monclk o m clock monitor pin 78 md_3 i h mode setting pin 79 x1 ? j1 clock (oscillation) output 80 x0 ? j1 clock (oscillation) input 82 x0a ? j2 sub clock (oscillation) input 83 x1a ? j2 sub clock (oscillation) output 84 initx i h external reset input pin 85 nmix i h non-maskable interrupt input pin 92 p19_0 i/o a general-purpose input/output port sin4 data input pin of usart4 93 p19_1 i/o a general-purpose input/output port sot4 data output pin of usart4 94 p19_2 i/o a general-purpose input/output port sck4 clock input/output pin of usart4 ck4 external clock input pin of free-run timer 4 95 p19_4 i/o a general-purpose input/output port sin5 data input pin of usart5 96 p19_5 i/o a general-purpose input/output port sot5 data output pin of usart5 pin no. pin name i/o i/o circuit type [1] function
mb91460b series document number: 002-04608 rev. *a page 14 of 126 97 p19_6 i/o a general-purpose input/output port sck5 clock input/output pin of usart5 ck5 external clock input pin of free-run timer 5 98 p18_0 i/o a general-purpose input/output port sin6 data input pin of usart6 99 p18_1 i/o a general-purpose input/output port sot6 data output pin of usart6 100 p18_2 i/o a general-purpose input/output port sck6 clock input/output pin of usart6 ck6 external clock input pin of free-run timer 6 101 p18_4 i/o a general-purpose input/output port sin7 data input pin of usart7 102 p18_5 i/o a general-purpose input/output port sot7 data output pin of usart7 103 p18_6 i/o a general-purpose input/output port sck7 clock input/output pin of usart7 ck7 external clock input pin of free-run timer 7 104 alarm_0 o n alarm comparator input pin 110 to 117 p29_0 to p29_7 i/o b general-purpose input/output port an0 to an7 analog input pins of a/d converter 118 to 125 p28_0 to p28_7 i/o b general-purpose input/output port an8 to an15 analog input pins of a/d converter 128 p24_2 i/o a general-purpose input/output port int2 external interrupt input pin 129 p24_3 i/o a general-purpose input/output port int3 external interrupt input pin 130 to 133 p14_0 to p14_3 i/o a general-purpose input/output port icu0 to icu3 input capture input pins tin0 to tin3 external trigger input pins of reload timer ttg0/8 to ttg3/11 external tri gger input pins of ppg timer 134 to 137 p15_0 to p15_3 i/o a general-purpose input/output port ocu0 to ocu3 output compare output pins tot0 to tot3 reload timer output pins 138 to 143 p07_0 to p07_5 i/o b general-purpose input/output port a0 to a5 signal pins of external address bus (bit0 to bit5) pin no. pin name i/o i/o circuit type [1] function
mb91460b series document number: 002-04608 rev. *a page 15 of 126 3.1.1 power supply/ground pins pin no. pin name i/o function 1, 19, 37, 55, 73, 81, 86, 91, 109, 127 vss5 supply ground pins 54, 72, 90, 108, 126 vdd5 power supply pins 88, 89 vdd5r power supply pins for internal regulator 105 avss5 analog ground pin for a/d converter 107 avcc5 power supply pin for a/d converter 106 avrh5 reference power supply pin for a/d converter 87 vcc18c capacitor connection pin for internal regulator 18, 36, 144 vdd35 power supply pins fo r external bus part of i/o ring
mb91460b series document number: 002-04608 rev. *a page 16 of 126 3.2 mb91f467ba/466ba and mb91f465bb/464bb with md_3=0 pin no. pin name i/o i/o circuit type [1] function 2 to 3 p27_6 to p27_7 i/o b general-purpose input/output ports an22 to an23 analog input pins of a/d converter 4 to 11 p26_0 to p26_7 i/o b general-purpose input/output ports an24 to an31 analog input pins of a/d converter 12 to 15 p24_4 to p24_7 i/o a general-purpose input/output ports int4 to int7 external interrupt input pins 16 p21_0 i/o a general-purpose input/output ports sin0 data input pin of usart0 17 p21_1 i/o a general-purpose input/output ports sot0 data output pin of usart0 20 to 23 p14_4 to p14_7 i/o a general-purpose input/output ports icu4 to icu7 input capture input pins tin4 to tin7 external trigger input pins of reload timer ttg4/12 to ttg7/15 external tri gger input pins of ppg timer 24 to 27 p15_4 to p15_7 i/o a general-purpose input/output ports ocu4 to ocu7 output compare output pins tot4 to tot7 reload timer output pins 28 to 35 p17_0 to p17_7 i/o a general-purpose input/output ports ppg0 to ppg7 output pins of ppg timer 38 p20_0 i/o a general-purpose input/output ports sin2 data input pin of usart2 ain0 up/down counter input pin 39 p20_1 i/o a general-purpose input/output ports sot2 data output pin of usart2 bin0 up/down counter input pin 40 p20_2 i/o a general-purpose input/output ports sck2 clock input/output pin of usart2 zin0 up/down counter input pin ck2 external clock input pin of free-run timer 2 41 p20_4 i/o a general-purpose input/output ports sin3 data input pin of usart3 ain1 up/down counter input pin 42 p20_5 i/o a general-purpose input/output ports sot3 data output pin of usart3 bin1 up/down counter input pin 43 p20_6 i/o a general-purpose input/output ports sck3 clock input/output pin of usart3 zin1 up/down counter input pin ck3 external clock input pin of free-run timer 3
mb91460b series document number: 002-04608 rev. *a page 17 of 126 44 p24_0 i/o a general-purpose input/output ports int0 external interrupt input pin 45 p24_1 i/o a general-purpose input/output ports int1 external interrupt input pin 46 p23_0 i/o a general-purpose input/output ports rx0 rx input pin of can0 int8 external interrupt input pin 47 p23_1 i/o a general-purpose input/output ports tx0 tx output pin of can0 48 p23_2 i/o a general-purpose input/output ports rx1 rx input pin of can1 int9 external interrupt input pin 49 p23_3 i/o a general-purpose input/output ports tx1 tx output pin of can1 50 p23_4 i/o a general-purpose input/output ports rx2 rx input pin of can2 int10 external interrupt input pin 51 p23_5 i/o a general-purpose input/output ports tx2 tx output pin of can2 52 p23_6 i/o a general-purpose input/output ports mb91f467ba/ mb91f466ba: rx3 rx input pin of can3 int11 external interrupt input pin 53 p23_7 mb91f467ba/ mb91f466ba: tx3 i/o a general-purpose input/output ports tx output pin of can3 56 p22_0 i/o a general-purpose input/output port mb91f467ba/ mb91f466ba: rx4 rx input pin of can4 int12 external interrupt input pin 57 p22_1 i/o a general-purpose input/output port mb91f467ba/ mb91f466ba: tx4 tx output pin of can4 58 p22_2 i/o a general-purpose input/output port int13 external interrupt input pin mb91f467ba/ mb91f466ba: rx5 rx input pin of can5 59 p22_3 i/o a general-purpose input/output port mb91f467ba/ mb91f466ba: tx5 tx output pin of can5 pin no. pin name i/o i/o circuit type [1] function
mb91460b series document number: 002-04608 rev. *a page 18 of 126 60 p22_4 i/o c general-purpose input/output ports sda0 i 2 c bus data input/output pin (open drain) int14 external interrupt input pin 61 p22_5 i/o c general-purpose input/output ports scl0 i 2 c bus clock input/output pin (open drain) 62 p22_6 i/o c general-purpose input/output ports sda1 i 2 c bus data input/output pin (open drain) int15 external interrupt input pin 63 p22_7 i/o c general-purpose input/output ports scl1 i 2 c bus clock input/output pin (open drain) 64 to 67 p16_0 to p16_3 i/o a general-purpose input/output ports ppg8 to ppg11 output pins of ppg timer 68 p16_4 i/o a general-purpose input/output ports ppg12 output pins of ppg timer sga sga output pin of sound generator 69 p16_5 i/o a general-purpose input/output ports ppg13 output pins of ppg timer sgo sg0 output pin of sound generator 70 p16_6 i/o a general-purpose input/output ports ppg14 output pins of ppg timer 71 p16_7 i/o a general-purpose input/output ports ppg15 output pins of ppg timer atgx a/d converter external trigger input pin 74 to 76 md_0 to md_2 i g mode setting pins 77 monclk o m clock monitor pin 78 md_3 i h mode setting pins 79 x1 ? j1 clock (oscillation) output 80 x0 ? j1 clock (oscillation) input 82 x0a ? j2 sub clock (oscillation) input 83 x1a ? j2 sub clock (oscillation) output 84 initx i h external reset input pin 85 nmix i h non-maskable interrupt input pin 92 p19_0 i/o a general-purpose input/output ports sin4 data input pin of usart4 93 p19_1 i/o a general-purpose input/output ports sot4 data output pin of usart4 94 p19_2 i/o a general-purpose input/output ports sck4 clock input/output pin of usart4 ck4 external clock input pin of free-run timer 4 pin no. pin name i/o i/o circuit type [1] function
mb91460b series document number: 002-04608 rev. *a page 19 of 126 1. for information about the i/o circuit type, refer to ? i/o circuit types ?. 95 p19_4 i/o a general-purpose input/output ports sin5 data input pin of usart5 96 p19_5 i/o a general-purpose input/output ports sot5 data output pin of usart5 97 p19_6 i/o a general-purpose input/output ports sck5 clock input/output pin of usart5 ck5 external clock input pin of free-run timer 5 98 p18_0 i/o a general-purpose input/output ports sin6 data input pin of usart6 99 p18_1 i/o a general-purpose input/output ports sot6 data output pin of usart6 100 p18_2 i/o a general-purpose input/output ports sck6 clock input/output pin of usart6 ck6 external clock input pin of free-run timer 6 101 p18_4 i/o a general-purpose input/output ports sin7 data input pin of usart7 102 p18_5 i/o a general-purpose input/output ports sot7 data output pin of usart7 103 p18_6 i/o a general-purpose input/output ports sck7 clock input/output pin of usart7 ck7 external clock input pin of free-run timer 7 104 alarm_0 i n alarm comparator input pin 110 to 117 p29_0 to p29_7 i/o b general-purpose input/output ports an0 to an7 analog input pins of a/d converter 118 to 125 p28_0 to p28_7 i/o b general-purpose input/output ports an8 to an15 analog input pins of a/d converter 128 p24_2 i/o a general-purpose input/output ports int2 external interrupt input pin 129 p24_3 i/o a general-purpose input/output ports int3 external interrupt input pin 130 to 133 p14_0 to p14_3 i/o a general-purpose input/output ports icu0 to icu3 input capture input pins tin0 to tin3 external trigger input pins of reload timer ttg0/8 to ttg3/11 external tri gger input pins of ppg timer 134 to 137 p15_0 to p15_3 i/o a general-purpose input/output ports ocu0 to ocu3 output compare output pins tot0 to tot3 reload timer output pins 138 to 143 p27_0 to p27_5 i/o b general-purpose input/output ports an16 to an21 analog input pins of a/d converter pin no. pin name i/o i/o circuit type [1] function
mb91460b series document number: 002-04608 rev. *a page 20 of 126 3.2.1 power supply/ground pins 1. for information about the i/o circuit type, refer to ? i/o circuit types ?. pin no. pin name i/o function 1, 19, 37, 55, 73, 81, 86, 91, 109, 127 vss5 supply ground pins 54, 72, 90, 108, 126 vdd5 power supply pins 88, 89 vdd5r power supply pins for internal regulator 105 avss5 analog ground pin for a/d converter 107 avcc5 power supply pin for a/d converter 106 avrh5 reference power supply pin for a/d converter 87 vcc18c capacitor connection pin for internal regulator 18, 36, 144 vdd35 power supply pins fo r external bus part of i/o ring
mb91460b series document number: 002-04608 rev. *a page 21 of 126 4. i/o circuit types type circuit remarks a cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. b cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown r analog input pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown
mb91460b series document number: 002-04608 rev. *a page 22 of 126 c cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. d cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control data line standby control for input shutdown r analog input pull-up control pull- down control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown
mb91460b series document number: 002-04608 rev. *a page 23 of 126 e cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, and i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. f cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, and i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown r analog input pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown
mb91460b series document number: 002-04608 rev. *a page 24 of 126 g mask rom and eva device: cmos hysteresis input pin flash device: cmos input pin 12 v withstand (for md [2:0]) h cmos hysteresis input pin pull-up resistor value: 50 k ? approx. j1 high-speed oscillation circuit: programmable between oscillat ion mode (external crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (exter nal clock connected to x0 pin) feedback resistor = approx. 2 * 0.5 m ? . feedback resistor is grounded in the center when the oscillator is disabl ed or in fci mode. j2 low-speed oscillation circuit: feedback resistor = approx. 2 * 5 m ? . feedback resistor is grounded in the center when the oscillator is disabled. type circuit remarks r hysteresis inputs r pull-up resistor hysteresis inputs x1 x0 r r xout fci 0 1 fci or osc disable x1a x0a r r xout osc disable
mb91460b series document number: 002-04608 rev. *a page 25 of 126 k cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. lcd seg/com output l cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function) ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input lcd voltage input type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown lcd seg/com r pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown vlcd
mb91460b series document number: 002-04608 rev. *a page 26 of 126 m cmos level tri-state output (i ol = 5ma, i oh = -5ma) n analog input pin with protection type circuit remarks tri-state control data line analog input line
mb91460b series document number: 002-04608 rev. *a page 27 of 126 5. handling devices 5.1 preventing latch-up latch-up may occur in a cmos ic if a voltage higher than (v dd 5, v dd 35 or hv dd 5 [1] ) or less than (v ss 5 or hv ss 5 [1] ) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. if latch- up occurs, the power supply current increases rapidly, sometimes re sulting in thermal breakdown of the device. therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. note: 1. hv dd 5, hv ss 5 are available only on devices having stepper motor controller. 5.2 handling of unused input pins if unused input pins are left open, abnormal o peration may result. any unused input pins should be connected to pull-up or pull -down resistor (2k ? to 10k ? ) or enable internal pullup or pulldown resisters (pper/ppcr) before the input enable (porten) is activated by software. the mode pins md_x can be connected to v ss 5 or v dd 5 directly. unused alarm input pins can be connected to av ss 5 directly. 5.3 power supply pins in mb91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be a t the same potential are interconnected internally to prevent malf unctions such as latch-up. all of the power supply pins and gro und pins must be externally connected to the power supply and ground re spectively in order to reduce unnecessary radiation, to prev ent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. furthermore, the powe r supply pins and ground pins of the mb91460 series must be connected to the current supply source via a low impedance. it is also recommended to connect a ceramic capacitor of ap proximately 0.1 ? f as a bypass capacitor between power supply pin and ground pin near this device. this series has a built-in st ep-down regulator. connect a bypass capacitor of 4.7 ? f (use a x7r ceramic capacitator) to vcc18c pin for the regulator. 5.4 crystal oscillator circuit noise in proximity to the x0 (x0a) and x1 (x1a) pins can cause the device to operate abnormally. printed circuit boards should be designed so that the x0 (x0a) and x1 (x1a) pins, and crystal o scillator, as well as bypass capacitors connected to ground, are located near the device and ground. it is recommended that the printed circuit board layout be designed such that the x0 and x1 pins or x0a and x1a pins are surrounded by ground plane for the stable operation. please re quest the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device. 5.5 notes on using external clock when using the external clock, it is ne cessary to simultaneously supply the x0 (x0a) and the x1 (x1a) pins. in the described combination, x1 (x1a) should be supplied with a clock signal whic h has the opposite phase to the x0 (x0a) pins. at x0 and x1, a frequency up to 16 mhz is possible. figure 1. example of using opposite phase supply x0 (x0a) x1 (x1a)
mb91460b series document number: 002-04608 rev. *a page 28 of 126 5.6 mode pins (md_x) these pins should be connected directly to the power supply or ground pins. to prev ent the device from entering test mode accidentally due to noise, minimize the lengt hs of the patterns between each mode pin and power supply pin or ground pin on the printed circuit board as possible and connect them with low impedance. 5.7 notes on operating in pll clock mode if the oscillator is disconnected or the clock input stops when th e pll clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit of the pll. however, this self-running operation cannot be guaran teed. 5.8 pull-up control the ac standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
mb91460b series document number: 002-04608 rev. *a page 29 of 126 6. notes on debugger 6.1 execution of the reti command if single-step execution is used in an environment where an in terrupt occurs frequently, the co rresponding interrupt handling r outine will be executed repeatedly to the exclusion of other processing. this will prevent th e main routine and the handlers for low p riority level interrupts from being executed (for exam ple, if the time-base timer interrupt is enabled, stepping over the reti instruct ion will always break on the first line of the time-base timer interrupt handler). disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging. 6.2 break function if the range of addresses that cause a hardw are break (including event breaks) is set to the address of the current system stac k pointer or to an area that contains the stack pointer, execut ion will break after each instruct ion regardless of whether the us er program actually contains data access instructions. to prevent this, do not set (word) access to the area containing the address of the system stack poi nter as the target of the h ardware break (including an event breaks). 6.3 operand break it may cause malfunctions if a stack pointer exists in the area which is set as the dsu operand break. do not set the access to the areas containing the address of system stack pointer as a target of dat a event break. 6.4 notes on ps register as the ps register is processed in advance by some instru ctions, when the debugger is being used, the exception handling may result in execution breaking in an inte rrupt handling routine or the displayed val ues of the flags in the ps register being upd ated. as the microcontroller is designed to carry out reprocessing co rrectly upon returning from such an eit event,the operation befo re and after the eit always proceeds according to specification. the following behavior may occur if any of the following occurs in the instruction im mediately after a div0u/div0s instruction: (a) a user interrupt or nmi is accepted; (b) single-step execution is performed; (c) execution breaks due to a data event or from the emulator menu. 1. d0 and d1 flags are updated in advance. 2. an eit handling routine (user inte rrupt/nmi or emulator) is executed. 3. upon returning from the eit, the div0 u/div0s instruction is executed and the d0 and d1 flags are updated to the same values as those in 1. the following behavior occurs when an orccr, stilm, mov ri,ps instruction is executed to enable a user interrupt or nmi source while that interrupt is in the active state. 1. the ps register is updated in advance. 2. an eit handling routine (user inte rrupt/nmi or emulator) is executed. 3. upon returning from the eit, the above in structions are executed and the ps register is updated to the same value as in 1.
mb91460b series document number: 002-04608 rev. *a page 30 of 126 7. block diagram 7.1 mb91f467ba/466ba with md_3=1 ttg0/8 to ttg3/11 ppg8 to ppg15 tin0 to tin3 tot0 to tot3 ck4 to ck7 icu0 to icu3 ocu0 to ocu3 alarm_0 sda0 to sda1 scl0 to scl1 an0 to an15 atgx sga sg0 sin4 to sin7 sot4 to sot7 sck4 to sck7 rx0 to rx5 tx0 to tx5 r-bus 16 i-bus 32 d-bus 32 fr60 cpu core flash-cache 8 kbytes flash memory 1088 kbytes (mb91f467ba) 832 kbytes (mb91f466ba) id-ram 16 kbytes bus converter d-ram 24 kbytes bit search can 6 channels 32 <-> 16 bus adapter dmac 5 channels clock modulator clock monitor monclk interrupt controller int0 to int3, int8 to to int15 external interrupt 12 channels clock supervisor clock control ppg timer 8 channels reload timer 8 channels free-run timer 8 channels input capture 4 channels output compare 4 channels alarm comparator 1 channel lin-usart 4 channels 2 channels i c 2 real time clock a/d converter 16 channels sound generator 1 channel rdx wrx0 to wrx1 csx0 to csx1 a0 to a21 d16 to d31 external bus interface sysclk rdy
mb91460b series document number: 002-04608 rev. *a page 31 of 126 7.2 mb91f467ba/466ba with md_3=0 ain0 to ain1 bin0 to bin1 zin0 to zin1 ttg0/8 to ttg7/15 ppg0 to ppg15 tin0 to tin7 tot0 to tot7 ck2 to ck7 icu0 to icu7 ocu0 to ocu7 alarm_0 sda0 to sda1 scl0 to scl1 an0 to an31 atgx sga sg0 sin2 to sin7,sin0 sot2 to sot7,sot0 sck2 to sck7 rx0 to rx5 tx0 to tx5 r-bus 16 i-bus 32 d-bus 32 fr60 cpu core flash-cache 8 kbytes flash memory 1088 kbytes (mb91f467ba) 832 kbytes (mb91f466ba) id-ram 16 kbytes bus converter d-ram 24 kbytes bit search can 6 channels 32 <-> 16 bus adapter dmac 5 channels clock modulator clock monitor monclk interrupt controller int0 to int15 external interrupt 16 channels clock supervisor clock control ppg timer 16 channels reload timer 8 channels free-run timer 8 channels input capture 8 channels output compare 8 channels up/down counter 2 channels alarm comparator 1 channel lin-usart 7 channels 2 channels i c 2 real time clock a/d converter 32 channels sound generator 1 channel
mb91460b series document number: 002-04608 rev. *a page 32 of 126 7.3 mb91f465bb/464bb with md_3=1 ttg0/8 to ttg3/11 ppg8 to ppg15 tin0 to tin3 tot0 to tot3 ck4 to ck7 icu0 to icu3 ocu0 to ocu3 alarm_0 sda0 to sda1 scl0 to scl1 an0 to an15 atgx sga sg0 sin4 to sin7 sot4 to sot7 sck4 to sck7 rx0 to rx2 tx0 to tx2 r-bus 16 i-bus 32 d-bus 32 fr60 cpu core flash-cache 8 kbytes flash memory 544 kbytes (mb91f465bb) 416 kbytes (mb91f464bb) id-ram 16 kbytes bus converter d-ram 24 kbytes bit search can 3 channels 32 <-> 16 bus adapter dmac 5 channels clock modulator clock monitor monclk interrupt controller int0 to int3, int8 to to int15 external interrupt 12 channels clock supervisor clock control ppg timer 8 channels reload timer 8 channels free-run timer 8 channels input capture 4 channels output compare 4 channels alarm comparator 1 channel lin-usart 4 channels 2 channels i c 2 real time clock a/d converter 16 channels sound generator 1 channel rdx wrx0 to wrx1 csx0 to csx1 a0 to a21 d16 to d31 external bus interface sysclk rdy
mb91460b series document number: 002-04608 rev. *a page 33 of 126 7.4 mb91f465bb/464bb with md_3=0 ain0 to ain1 bin0 to bin1 zin0 to zin1 ttg0/8 to ttg7/15 ppg0 to ppg15 tin0 to tin7 tot0 to tot7 ck2 to ck7 icu0 to icu7 ocu0 to ocu7 alarm_0 sda0 to sda1 scl0 to scl1 an0 to an31 atgx sga sg0 sin2 to sin7,sin0 sot2 to sot7,sot0 sck2 to sck7 rx0 tx0 r-bus 16 i-bus 32 d-bus 32 fr60 cpu core flash-cache 8 kbytes flash memory 416 kbytes (mb91f464hb) id-ram 16 kbytes bus converter d-ram 16kbytes bit search can 1 channel 32 <-> 16 bus adapter dmac 5 channels clock modulator clock monitor monclk interrupt controller int0 to int15 external interrupt 16 channels clock supervisor clock control ppg timer 16 channels reload timer 8 channels free-run timer 8 channels input capture 8 channels output compare 8 channels up/down counter 2 channels alarm comparator 1 channel lin-usart 7 channels 2 channels i c 2 real time clock a/d converter 32 channels sound generator 1 channel
mb91460b series document number: 002-04608 rev. *a page 34 of 126 8. cpu and control unit the fr family cpu is a high performance core that is designed based on the risc architecture with advanced instructions for embedded applications. 8.1 features adoption of risc architecture basic instruction: 1 instruction per cycle general-purpose registers: 32-bit 16 registers 4 gbytes linear memory space multiplier installed 32-bit 32-bit mult iplication: 5 cycles 16-bit 16-bit mult iplication: 3 cycles enhanced interrupt processing function quick response speed (6 cycles) multiple-interrupt support level mask function (16 levels) enhanced instructions for i/o operation memory-to-memory transfer instruction bit processing instruction basic instruction word length: 16 bits low-power consumption sleep mode/stop mode 8.2 internal architecture the fr family cpu uses the harvard architecture in which the instruction bus and data bus are independent of each other. a 32-bit ? 16-bit buffer is connected to the 32-bi t bus (d-bus) to provide an interface between the cpu and peripheral resources. a harvard ? princeton bus converter is connected to both the i-bus and d-bus to provid e an interface between the cpu and the bus controller.
mb91460b series document number: 002-04608 rev. *a page 35 of 126 8.3 programming model 8.3.1 basic programming model ilm scr ccr fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 pc rs rp tbr ssp usp mdl mdh . . . . . . 32 bits initial value general-purpose registers program counter program status table base register return pointer system stack pointer user stack pointer multiply & divide registers
mb91460b series document number: 002-04608 rev. *a page 36 of 126 8.4 registers 8.4.1 general-purpose register registers r0 to r15 are general-purpose regi sters. these registers can be used as accu mulators for computation operations and a s pointers for memory access. of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications . r13 : virtual accumulator r14 : frame pointer r15 : stack pointer initial values at reset are undefined for r0 to r14. the value for r15 is 00000000 h (ssp value). 8.4.2 ps (program status) this register holds the program status, and is divided into three parts, ilm, scr, and ccr. all undefined bits (-) in the diagram are reserved bits. the read values are always ?0?. write access to these bits is invalid. fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 . . . . . . 32 bits initial value bit position bit 20 bit 0 bit 7 bit 8 bit 10 bit 16 ilm scr ccr bit 31
mb91460b series document number: 002-04608 rev. *a page 37 of 126 8.4.3 ccr (condition code register) sv: supervisor flag s: stack flag i: interrupt enable flag n: negative enable flag z: zero flag v: overflow flag c: carry flag 8.4.4 scr (system condition register) flag for step division (d1, d0) this flag stores interim data dur ing execution of step division. step trace trap flag (t) this flag indicates whether the step trace trap is enabled or disabled. the step trace trap function is used by emul ators. when an emulator is in use, it ca nnot be used in execut ion of user programs. 8.4.5 ilm (interrupt level mask register) this register stores interrupt level mask values, and the values stored in ilm4 to ilm0 are used for level masking. the register is initialized to value ?01111 b ? at reset. 8.4.6 pc (program counter) the program counter indicates the address of the instruction that is being executed. the initial value at reset is undefined. - 000xxxx b bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 c v z n i s sv initial value bit 10 bit 8 bit 9 d1 d0 t xx0 b initial value bit 18 bit 16 bit 17 ilm2 ilm1 ilm0 01111 b ilm3 ilm4 bit 20 bit 19 initial value bit 0 bit 31 xxxxxxxx h initial value
mb91460b series document number: 002-04608 rev. *a page 38 of 126 8.4.7 tbr (table base register) the table base register stores the starting addre ss of the vector table used in eit processing. the initial value at reset is 000ffc00 h . 8.4.8 rp (return pointer) the return pointer stores the address for return from subroutines. during execution of a call instruction, the pc value is transferred to this rp register. during execution of a ret instruction, the conten ts of the rp register are transferred to pc. the initial value at reset is undefined. 8.4.9 usp (user stack pointer) the user stack pointer, when the s flag is ?1?, this register functions as the r15 register. the usp register can also be explicitly specified. the initial value at reset is undefined. this register cannot be used with reti instructions. 8.4.10 multiply & divide registers these registers are for multiplication and division, and are each 32 bits in length. the initial value at reset is undefined. bit 0 bit 31 000ffc00 h initial value bit 0 bit 31 xxxxxxxx h initial value bit 0 bit 31 xxxxxxxx h initial value bit 0 mdl bit 31 mdh
mb91460b series document number: 002-04608 rev. *a page 39 of 126 9. embedded program/data memory (flash) 9.1 flash features mb91f467ba: 1088 kbytes (16 64 kbytes + 8 8 kbytes = 8.5 mbits) mb91f466ba: 832 kbytes (12 64 kbytes + 8 8 kbytes = 6.5 mbits) mb91f465bb: 544 kbytes (8 64 kb ytes + 4 8 kbytes = 4.25 mbits) mb91f464bb: 416 kbytes (6 64 kb ytes + 4 8 kbytes = 3.25 mbits) programmable wait states for read/write access flash and boot security with security vector at 0x0014:8000 - 0x0014:800f boot security basic specification: same as mbm29lv400tc (e xcept size and part of sector configuration) 9.2 operation modes 9.2.1 64-bit cpu mode (availab le on mb91f467ba/466ba only) : cpu reads and executes programs in word (32-bit) length units. flash writing is not possible. actual flash memory access is performed in d-word (64-bit) length units. 9.2.2 32-bit cpu mode: cpu reads and executes programs in word (32-bit) length units. actual flash memory access is performed in word (32-bit) length units. 9.2.3 16-bit cpu mode: cpu reads and writes in half-word (16-bit) length units. program execution from the flash is not possible. actual flash memory access is performed in word (16-bit) length units. 9.2.4 flash memory mode (externa l access to flash memory enabled) note : the operation mode of the flash memory can be selected usi ng a boot-rom function. the func tion start address is 0xbf60. the parameter description is given in the hardware manual in chapter 54.6 "flash access mode switching".
mb91460b series document number: 002-04608 rev. *a page 40 of 126 9.3 flash access in cpu mode 9.3.1 flash configuration 9.3.1.1 flash memory map mb91f467ba roms1 roms0 addr+6 roms5 roms4 roms6 roms7 roms3 roms2 dat[31:16] dat[15:0] dat[31:0] dat[31:0] dat[31:16] dat[15:0] 16bit read/write 32bit read/write dat[63:0] 64bit read addr+7 addr+2 sa0 (8kb) sa16 (64kb) sa10 (64kb) sa21 (64kb) sa19 (64kb) address 0014:ffffh 0014:c000h 0014:bfffh 0014:8000h sa7 (8kb) sa5 (8kb) sa3 (8kb) sa1 (8kb) sa23 (64kb) sa6 (8kb) sa4 (8kb) sa2 (8kb) sa22 (64kb) sa20 (64kb) 0013:ffffh 0012:0000h 0011:ffffh 0010:0000h sa18 (64kb) 0014:7fffh 0014:4000h 0014:3fffh 0014:0000h 000f:ffffh 000e:0000h sa15 (64kb) 000d:ffffh 000c:0000h 000b:ffffh 000a:0000h addr+5 sa11 (64kb) sa8 (64kb) sa9 (64kb) addr+0 addr+1 addr+3 addr+4 0009:ffffh 0008:0000h 0007:ffffh 0006:0000h 0005:ffffh 0004:0000h sa17 (64kb) sa14 (64kb) sa12 (64kb) sa13 (64kb)
mb91460b series document number: 002-04608 rev. *a page 41 of 126 9.3.1.2 flash memory map mb91f466ba roms7 addr+3 addr+4 0009:ffffh 0008:0000h 0007:ffffh 0006:0000h 0005:ffffh 0004:0000h sa12 (64kb) sa13 (64kb) 0014:7fffh 0014:4000h 0014:3fffh 0014:0000h 000f:ffffh 000e:0000h sa15 (64kb) 000d:ffffh 000c:0000h 000b:ffffh 000a:0000h sa17 (64kb) sa14 (64kb) sa22 (64kb) sa20 (64kb) 0013:ffffh 0012:0000h 0011:ffffh 0010:0000h sa18 (64kb) sa7 (8kb) sa5 (8kb) sa3 (8kb) sa1 (8kb) sa23 (64kb) sa6 (8kb) sa4 (8kb) sa2 (8kb) addr 0014:ffffh 0014:c000h 0014:bfffh 0014:8000h addr+7 addr+2 sa0 (8kb) sa16 (64kb) sa10 (64kb) sa21 (64kb) sa19 (64kb) dat[15:0] 16bit read/write 32bit read 64bit read roms2 dat[31:16] dat[15:0] dat[31:0] dat[31:0] dat[31:16] roms1 roms0 addr+6 roms5 roms4 roms6 roms3 addr+5 sa11 (64kb) sa8 (64kb) sa9 (64kb) addr+0 addr+1 legend memory not available in this area memory available in this area dat[63:0]
mb91460b series document number: 002-04608 rev. *a page 42 of 126 9.3.1.3 flash memory map mb91f465bb roms7 legend memory not available in this area addr+3 addr+4 0009:ffffh 0008:0000h 0007:ffffh 0006:0000h 0005:ffffh 0004:0000h sa12 (64kb) sa13 (64kb) 0014:7fffh 0014:4000h 0014:3fffh 0014:0000h 000f:ffffh 000e:0000h sa15 (64kb) 000d:ffffh 000c:0000h 000b:ffffh 000a:0000h sa17 (64kb) sa14 (64kb) sa22 (64kb) sa20 (64kb) 0013:ffffh 0012:0000h 0011:ffffh 0010:0000h sa18 (64kb) sa7 (8kb) sa5 (8kb) sa3 (8kb) sa1 (8kb) sa23 (64kb) sa6 (8kb) sa4 (8kb) sa2 (8kb) addr 0014:ffffh 0014:c000h 0014:bfffh 0014:8000h addr+7 addr+2 sa0 (8kb) sa16 (64kb) sa10 (64kb) sa21 (64kb) sa19 (64kb) dat[15:0] 16bit read/write 32bit read roms2 dat[31:16] dat[15:0] dat[31:0] dat[31:0] dat[31:16] roms1 roms0 addr+6 roms5 roms4 roms6 roms3 memory available in this area addr+5 sa11 (64kb) sa8 (64kb) sa9 (64kb) addr+0 addr+1
mb91460b series document number: 002-04608 rev. *a page 43 of 126 9.3.1.4 flash memory map mb91f464bb roms7 addr+3 addr+4 0009:ffffh 0008:0000h 0007:ffffh 0006:0000h 0005:ffffh 0004:0000h sa12 (64kb) sa13 (64kb) 0014:7fffh 0014:4000h 0014:3fffh 0014:0000h sa15 (64kb) 000d:ffffh 000c:0000h 000b:ffffh 000a:0000h sa17 (64kb) sa14 (64kb) sa22 (64kb) sa20 (64kb) 0013:ffffh 0012:0000h 0011:ffffh 0010:0000h sa18 (64kb) 000f:ffffh 000e:0000h sa7 (8kb) sa5 (8kb) sa3 (8kb) sa1 (8kb) sa23 (64kb) sa6 (8kb) sa4 (8kb) sa2 (8kb) address 0014:ffffh 0014:c000h 0014:bfffh 0014:8000h addr+7 addr+2 sa0 (8kb) sa16 (64kb) sa10 (64kb) sa21 (64kb) sa19 (64kb) dat[15:0] 16bit read/write 32bit read legend memory not available in this area roms2 dat[31:16] dat[15:0] dat[31:0] dat[31:0] dat[31:16] roms1 roms0 addr+6 roms5 roms4 roms6 roms3 memory available in this area addr+5 sa11 (64kb) sa8 (64kb) sa9 (64kb) addr+0 addr+1
mb91460b series document number: 002-04608 rev. *a page 44 of 126 9.3.2 flash access timing settings in cpu mode the following tables list all settings for a given maximum core frequency (through the setting of clkb or maximum clock modulation) for flash read and write access. 9.3.2.1 flash read timing settings (synchronous read) 9.3.2.2 flash write timing settings (synchronous write) core clock (clkb) atd aleh eq wexh wtc remark to 24 mhz 0 0 0 - 1 to 48 mhz 0 0 1 - 2 to 96 mhz 1 1 3 - 4 to 100 mhz 1 1 3 - 4 not available on mb91f467ba/mb91f466ba core clock (clkb) atd aleh eq wexh wtc remark to 16 mhz 0 - - 0 3 to 32 mhz 0 - - 0 4 to 48 mhz 0 - - 0 5 to 64 mhz 1 - - 0 6 to 96 mhz 1 - - 0 7 to 100 mhz 1 - - 0 7 not available on mb91f467ba/mb91f466ba
mb91460b series document number: 002-04608 rev. *a page 45 of 126 9.3.3 address mapping from cpu to parallel programming mode the following tables show the calculation from cpu addresses to flash macro addresses which are used in parallel programming. 9.3.3.1 address mapping mb91f467ba note : fa result is without 20:0000h offset for parallel flash programming . set offset by keeping fa[21] = 1 as described in sectio n ?parallel flash programming mode ?. 9.3.3.2 address mapping mb91f466ba note: fa result is without 20:0000h of fset for parallel flash programming . set offset by keeping fa[21] = 1 as described in section ?parallel flash programming mode ?. cpu address (addr) condition flash sectors fa (flash address) calculation 14:0000h to 14:ffffh addr[2]==0 sa0, sa2, sa4, sa6 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h 14:0000h to 14:ffffh addr[2]==1 sa1, sa3, sa5, sa7 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 05:0000h 04:0000h to 13:ffffh addr[2]==0 sa8, sa10, sa12, sa14, sa16, sa18, sa20, sa22 (64 kbyte) fa := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 0c:0000h 04:0000h to 13:ffffh addr[2]==1 sa9, sa11, sa13, sa15, sa17, sa19, sa21, sa23 (64 kbyte) fa := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4 + 0c:0000h cpu address (addr) condition flash sectors fa (flash address) calculation 14:0000h to 14:ffffh addr[2]==0 sa0, sa2, sa4, sa6 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h 14:0000h to 14:ffffh addr[2]==1 sa1, sa3, sa5, sa7 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (ad- dr/2)%4 + addr%4 - 05:0000h 04:0000h to 0f:ffffh addr[2]==0 sa8, sa10, sa12, sa14, sa16, sa18 (64 kbyte) fa := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + ad- dr%4 + 0c:0000h 04:0000h to 0f:ffffh addr[2]==1 sa9, sa11, sa13, sa15, sa17, sa19 (64 kbyte) fa := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (ad- dr/2)%4 + addr%4 + 0c:0000h
mb91460b series document number: 002-04608 rev. *a page 46 of 126 9.3.3.3 address mapping mb91f465bb note : fa result is without 20:0000h offset for parallel flash programming . set offset by keeping fa[21] = 1 as described in sectio n ?parallel flash programming mode ?. 9.3.3.4 address mapping mb91f464bb note : fa result is without 20:0000h offset for parallel flash programming . set offset by keeping fa[21] = 1 as described in sectio n ?parallel flash programming mode ?. cpu address (addr) condition flash sectors fa (flash address) calculation 14:8000h to 14:ffffh addr[2]==0 sa4, sa6 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 0d:0000h 14:8000h to 14:ffffh addr[2]==1 sa5, sa7 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 0d:0000h 08:0000h to 0f:ffffh addr[2]==0 sa12, sa14, sa16, sa18 (64 kbyte) fa := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 08:0000h to 0f:ffffh addr[2]==1 sa13, sa15, sa17, sa19 (64 kbyte) fa := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4 cpu address (addr) condition flash sectors fa (flash address) calculation 14:8000h to 14:ffffh addr[2]==0 sa4, sa6 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 0d:0000h 14:8000h to 14:ffffh addr[2]==1 sa5, sa7 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 0d:0000h 0a:0000h to 0f:ffffh addr[2]==0 sa14, sa16, sa18 (64 kbyte) fa := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 0a:0000h to 0f:ffffh addr[2]==1 sa15, sa17, sa19 (64 kbyte) fa := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4
mb91460b series document number: 002-04608 rev. *a page 47 of 126 9.4 parallel flas h programming mode 9.4.1 flash configuration in pa rallel flash programming mode 9.4.1.1 parallel flash programming mode (md[2:0] = 111): mb91f467ba mb91f466ba remark: always keep fa[0] = 0 and fa[21] = 1 16bit write mode dq[15:0] dq[15:0] sa20 (64kb) sa19 (64kb) sa18 (64kb) fa[21:0] 003e:ffffh 003e:0000h 003d:ffffh 003d:0000h 003f:ffffh 003f:0000h sa23 (64kb) sa22 (64kb) sa21 (64kb) 003c:ffffh 003c:0000h 003b:ffffh 003b:0000h 003a:ffffh 003a:0000h 0039:ffffh 0039:0000h sa17 (64kb) 0038:ffffh 0038:0000h 0037:ffffh 0037:0000h sa16 (64kb) sa15 (64kb) 0036:ffffh 0036:0000h 0035:ffffh 0035:0000h sa14 (64kb) sa13 (64kb) 0034:ffffh 0034:0000h 0033:ffffh 0033:0000h sa12 (64kb) sa11 (64kb) 0032:ffffh 0032:0000h 0031:ffffh 0031:0000h sa10 (64kb) sa9 (64kb) 0030:ffffh 0030:0000h 002f:ffffh 002f:e000h sa8 (64kb) sa7 (8kb) 002f:7fffh 002f:6000h sa4 (8kb) sa3 (8kb) 002f:dfffh 002f:c000h 002f:bfffh 002f:a000h sa6 (8kb) sa5 (8kb) 002f:1fffh 002f:0000h sa0 (8kb) fa[1:0]=00 fa[1:0]=10 002f:5fffh 002f:4000h 002f:3fffh 002f:2000h sa2 (8kb) sa1 (8kb) 002f:9fffh 002f:8000h 16bit write mode dq[15:0] dq[15:0] sa20 (64kb) sa19 (64kb) sa18 (64kb) fa[21:0] sa23 (64kb) sa22 (64kb) sa21 (64kb) 003b:ffffh 003b:0000h 003a:ffffh 003a:0000h 0039:ffffh 0039:0000h sa17 (64kb) 0038:ffffh 0038:0000h 0037:ffffh 0037:0000h sa16 (64kb) sa15 (64kb) 0036:ffffh 0036:0000h 0035:ffffh 0035:0000h sa14 (64kb) sa13 (64kb) 0034:ffffh 0034:0000h 0033:ffffh 0033:0000h sa12 (64kb) sa11 (64kb) 0032:ffffh 0032:0000h 0031:ffffh 0031:0000h sa10 (64kb) sa9 (64kb) 0030:ffffh 0030:0000h 002f:ffffh 002f:e000h sa8 (64kb) sa7 (8kb) 002f:7fffh 002f:6000h sa4 (8kb) sa3 (8kb) 002f:dfffh 002f:c000h 002f:bfffh 002f:a000h sa6 (8kb) sa5 (8kb) 002f:1fffh 002f:0000h sa0 (8kb) fa[1:0]=00 fa[1:0]=10 002f:5fffh 002f:4000h 002f:3fffh 002f:2000h sa2 (8kb) sa1 (8kb) 002f:9fffh 002f:8000h
mb91460b series document number: 002-04608 rev. *a page 48 of 126 mb91f465bb mb91f464bb remark: always keep fa[0] = 0 and fa[21] = 1 sa0 (8kb) fa[1:0]=00 fa[1:0]=10 sa2 (8kb) sa1 (8kb) 0017:9fffh 0017:8000h sa4 (8kb) sa3 (8kb) 0017:dfffh 0017:c000h 0017:bfffh 0017:a000h sa6 (8kb) sa5 (8kb) 0017:ffffh 0017:e000h sa8 (64kb) sa7 (8kb) sa10 (64kb) sa9 (64kb) 0018:ffffh 0018:0000h sa12 (64kb) sa11 (64kb) 001a:ffffh 001a:0000h 0019:ffffh 0019:0000h sa14 (64kb) sa13 (64kb) 001c:ffffh 001c:0000h 001b:ffffh 001b:0000h sa16 (64kb) sa15 (64kb) 001e:ffffh 001e:0000h 001d:ffffh 001d:0000h sa17 (64kb) 001f:ffffh 001f:0000h sa19 (64kb) sa18 (64kb) dq[15:0] dq[15:0] remark: always keep fa[0] = 0 and fa[20] = 1 16bit write mode legend memory available in this area memory not available in this area fa[20:0] fa[20:0] sa0 (8kb) fa[1:0]=00 fa[1:0]=10 sa2 (8kb) sa1 (8kb) 0017:9fffh 0017:8000h sa4 (8kb) sa3 (8kb) 0017:dfffh 0017:c000h 0017:bfffh 0017:a000h sa6 (8kb) sa5 (8kb) 0017:ffffh 0017:e000h sa8 (64kb) sa7 (8kb) sa10 (64kb) sa9 (64kb) sa12 (64kb) sa11 (64kb) 001a:ffffh 001a:0000h sa14 (64kb) sa13 (64kb) 001c:ffffh 001c:0000h 001b:ffffh 001b:0000h sa16 (64kb) sa15 (64kb) 001e:ffffh 001e:0000h 001d:ffffh 001d:0000h sa17 (64kb) 001f:ffffh 001f:0000h sa19 (64kb) sa18 (64kb) dq[15:0] dq[15:0] remark: always keep fa[0] = 0 and fa[20] = 1 16bit write mode legend memory available in this area memory not available in this area
mb91460b series document number: 002-04608 rev. *a page 49 of 126 9.4.2 pin connections in parallel programming mode resetting after setting the md[2:0] pins to [111] will halt cpu functioning. at this time, the flash memory's interface circuit enables direct control of the flash memory unit from external pins by directly linking some of the signals to gp-ports. please see tabl e below for signal mapping. in this mode, the flash memory appears to the external pins as a stand-alone unit. this mode is generally set when writing/eras ing using the parallel flash programmer. in this mode, all operations of the 8.5 mbits flash memory's auto algorithms are available . table 1. correspondence between mbm29lv400tc and flash memory control signals mbm29lv400tce xternal pins fr-cpu mode mb91f467ba/466ba/f465bb/f464bb external pins comment flash memory mode normal function pin number - initx - initx 84 reset - frstx gp16_6 70 - - md2 md2 76 set to ?1? - - md1 md1 75 set to ?1? - - md0 md0 74 set to ?1? ry/by fmcs:rdy bit ry/byx gp18_2 100 byte internally fixed to ?h? bytex gp16_4 68 we internal control signal + control via interface circuit wex gp16_7 71 oe oex gp07_7 3 ce cex gp07_6 2 - atdin gp18_6 103 set to ?0? - eqin gp18_5 102 set to ?0? - testx gp16_5 69 set to ?1? - rdyi gp18_4 101 set to ?0? a-1 internal address bus fa0 gp05_5 17 set to ?0? a0 to a3 fa1 to fa4 gp19_0 to gp19_2, gp19_4 92 to 95 a4 to a7 fa5 to fa8 gp19_5 to gp19_6, gp18_0 to gp18_1 96 to 99 a8 to a11 fa9 to fa12 gp06_0 to gp06_3 4 to 7 a12 to a15 fa13 to fa16 gp06_4 to gp06_7 8 to 11 a16 to a18 fa17 to fa19 gp05_0 to gp05_2 12 to 14 a19 fa20 gp05_3 15 see note [1] 1. a19 is used as address bit on mb91f467ba/f466ba. for mb91f465bb/f464bb, set this pin to ?1?. - fa21 gp05_4 16 see note [2] 2. for mb91f467ba/f466ba, set this pin to ?1?. for mb91f465bb/f464bb, this pin can be left open. dq0 to dq7 internal data bus dq0 to dq7 gp00_0 to gp00_7 28 to 35 dq8 to dq15 dq8 to dq15 gp01_0 to gp01_7 20 to 27
mb91460b series document number: 002-04608 rev. *a page 50 of 126 9.5 poweron sequence in parallel programming mode the flash memory can be accessed in programming mode after a ce rtain wait time, which is needed for security vector fetch: minimum wait time after vdd5/vdd5r power on: 2.76 ms minimum wait time afte r initx rising: 1.0 ms 9.6 flash security 9.6.1 vector addresses two flash security vectors (fsv1, fsv2) are located parallel to the boot security vectors (bsv1, bsv2) controlling the protecti on functions of the flash security module: fsv1: 0x14:8000 bsv1: 0x14:8004 fsv2: 0x14:8008 bsv2: 0x14:800c 9.6.2 security vector fsv1 the setting of the flash security vector fsv1 is responsibl e for the read and write protection modes and the individual write protection of the 8 kbytes sectors. 9.6.2.1 fsv1 (bit31 to bit16) the setting of the flash security vector fsv1 bits [31: 16] is responsible for the r ead and write protection modes. table 2. explanation of the bits in the flash security vector fsv1[31:16] fsv1[31:19] fsv1[18] write protection level fsv1[17] write protection fsv1[16] read protection flash security mode set all to ?0? set to ?0? set to ?0? set to ?1? read protection (all device modes, except intvec mode md[2:0]=?000?) set all to ?0? set to ?0? set to ?1? set to ?0? write protection (all device modes, without exception) set all to ?0? set to ?0? set to ?1? set to ?1? read protection (all device modes, except intvec mode md[2:0]=?000?) and write protection (all device modes) set all to ?0? set to ?1? set to ?0? set to ?1? read protection (all device modes, except intvec mode md[2:0]=?000?) set all to ?0? set to ?1? set to ?1? set to ?0? write protection (all device modes, except intvec mode md[2:0]=?000?) set all to ?0? set to ?1? set to ?1? set to ?1? read protection (all device modes, except intvec mode md[2:0]=?000?) and write protection (all device modes except intvec mode md[2:0]=?000?)
mb91460b series document number: 002-04608 rev. *a page 51 of 126 9.6.2.2 fsv1 (bit15 to bit0) mb91f467ba/466ba the setting of the flash security vector fsv1 bits [15:0] is responsible for the individual write protection of the 8 kbytes se ctors. it is only evaluated if write pr otection bit fsv1[17] is set. table 3. explanation of the bits in the flash security vector fsv1[15:0] note: it is mandatory to always set the sector wh ere the flash security vectors fsv1 and fs v2 are located to wr ite protected (here sector sa4). otherwise it is possible to overwrite the security vector to a setting where it is possible to either read out the flash content or manipulate data by writing. see section ?flash acce ss in cpu mode? for an overview about the sector organisation of the flash memory. 9.6.2.3 fsv1 (bit15 to bit0) mb91f465bb/464bb the setting of the flash security vector fsv1 bits [15:0] is responsible for the individual write protection of the 8 kbytes se ctors. it is only evaluated if write pr otection bit fsv1[17] is set. table 4. explanation of the bits in the flash security vector fsv1[15:0] note : it is mandatory to always set the sector where the flash security vectors fsv1 and fsv2 are located to write prot ected (here sector sa4). otherwise it is possible to overwrite the security vector to a setting where it is possible to either read out the flash content or manipulate data by writing. see section ?flash access in cpu mode ? for an overview about the sector organisation of the flash memory. fsv1 bit sector enable write protection disable write protection comment fsv1[0] sa0 set to ?0? set to ?1? fsv1[1] sa1 set to ?0? set to ?1? fsv1[2] sa2 set to ?0? set to ?1? fsv1[3] sa3 set to ?0? set to ?1? fsv1[4] sa4 set to ?0? ? write protection is manda- tory! fsv1[5] sa5 set to ?0? set to ?1? fsv1[6] sa6 set to ?0? set to ?1? fsv1[7] sa7 set to ?0? set to ?1? fsv1[15:8] ??? not available fsv1 bit sector enable write protection disable write protection comment fsv1[3:0] ??? not available fsv1[4] sa4 set to ?0? ? write protection is manda- tory! fsv1[5] sa5 set to ?0? set to ?1? fsv1[6] sa6 set to ?0? set to ?1? fsv1[7] sa7 set to ?0? set to ?1? fsv1[15:8] ??? not available
mb91460b series document number: 002-04608 rev. *a page 52 of 126 9.6.3 security vector fsv2 mb91f467ba/466ba the setting of the flash security vector fsv2 bits [31:0] is responsible for the individual writ e protection of the 64 kbyte se ctors. it is only evaluated if write pr otection bit fsv1[17] is set. table 5. explanation of the bits in the flash security vector fsv2[31:0] note: see section ?flash access in cpu mode? for an overvi ew about the sector organisation of the flash memory. 9.6.4 security vector fsv2 mb91f465bb/464bb the setting of the flash security vector fsv2 bits [31:0] is responsible for the individual writ e protection of the 64 kbyte se ctors. it is only evaluated if write pr otection bit fsv1[17] is set. table 6. explanation of the bits in the flash security vector fsv2[31:0] note: see section ?flash access in cpu mode? for an overview about the sector organisation of the flash memory. fsv2 bit sector enable write protection disable write protection comment fsv2[0] sa8 set to ?0? set to ?1? fsv2[1] sa9 set to ?0? set to ?1? fsv2[2] sa10 set to ?0? set to ?1? fsv2[3] sa11 set to ?0? set to ?1? fsv2[4] sa12 set to ?0? set to ?1? fsv2[5] sa13 set to ?0? set to ?1? fsv2[6] sa14 set to ?0? set to ?1? fsv2[7] sa15 set to ?0? set to ?1? fsv2[8] sa16 set to ?0? set to ?1? fsv2[9] sa17 set to ?0? set to ?1? fsv2[10] sa18 set to ?0? set to ?1? fsv2[11] sa19 set to ?0? set to ?1? fsv2[12] sa20 (mb91f467ba) set to ?0? set to ?1? fsv2[13] sa21 (mb91f467ba) set to ?0? set to ?1? fsv2[14] sa22 (mb91f467ba) set to ?0? set to ?1? fsv2[15] sa23 (mb91f467ba) set to ?0? set to ?1? fsv2[31:16] ? set to ?0? set to ?1? not available fsv2 bit sector enable write protection disable write protection comment fsv2[3:0] ??? not available fsv2[4] sa12 (mb91f465bb) set to ?0? set to ?1? fsv2[5] sa13 (mb91f465bb) set to ?0? set to ?1? fsv2[6] sa14 set to ?0? set to ?1? fsv2[7] sa15 set to ?0? set to ?1? fsv2[8] sa16 set to ?0? set to ?1? fsv2[9] sa17 set to ?0? set to ?1? fsv2[10] sa18 set to ?0? set to ?1? fsv2[11] sa19 set to ?0? set to ?1? fsv2[31:12] ??? not available
mb91460b series document number: 002-04608 rev. *a page 53 of 126 10. memory space the fr family has 4 gbytes of logical address space (2 32 addresses) available to the cpu by linear access. direct addressing area the following address space area is used for i/o. this area is called direct addressing area, and the address of an operand can be specified directly in an instruction. the size of directly addressable area depends on the le ngth of the data being accessed as shown below. byte data access: 000 h to 0ff h half word access: 000 h to 1ff h word data access: 000 h to 3ff h
mb91460b series document number: 002-04608 rev. *a page 54 of 126 11. memory maps 11.1 mb91f467ba, mb91f466ba mb91f467ba mb91f466ba 00000000 h 00000400 h i/o (direct addressing area) i/o 00002000 h 00004000 h flash-cache (8 kbytes) 00001000 h dma 00006000 h 00007000 h flash memory control 00008000 h 0000b000 h boot rom (4 kbytes) 0000c000 h can 0000d000 h 0002a000 h d-ram (0 wait, 24 kbytes) 00030000 h id-ram (16 kbytes) 00034000 h 00040000 h flash memory (1088 kbytes) 00150000 h 00180000 h external bus area 00500000 h external data bus ffffffff h note: access prohibited areas 00000000 h 00000400 h i/o (direct addressing area) i/o 00002000 h 00004000 h flash-cache (8 kbytes) 00001000 h dma 00006000 h 00007000 h flash memory control 00008000 h 0000b000 h boot rom (4 kbytes) 0000c000 h can 0000d000 h 0002a000 h d-ram (0 wait, 24 kbytes) 00030000 h id-ram (16 kbytes) 00034000 h 00040000 h flash memory (768 kbytes) 00150000 h 00180000 h external bus area 00500000 h external data bus ffffffff h note: access prohibited areas 00140000 h flash memory (64 kbytes) 00100000 h external bus area 00080000 h
mb91460b series document number: 002-04608 rev. *a page 55 of 126 11.2 mb91f465bb, mb91f464bb mb91f465bb mb91f464bb 00000000 h 00000400 h i/o (direct addressing area) i/o 00002000 h 00004000 h flash-cache (8 kbytes) 00001000 h dma 00006000 h 00007000 h flash memory control 00008000 h 0000b000 h boot rom (4 kbytes) 0000c000 h can 0000d000 h 0002a000 h d-ram (0 wait, 24 kbytes) 00030000 h id-ram (16 kbytes) 00034000 h 00040000 h flash memory (512 kbytes) 00150000 h 00180000 h external bus area 00500000 h external data bus ffffffff h note: access prohibited areas 00148000 h flash memory (32 kbytes) 00100000 h external bus area 00080000 h external bus area 00000000 h 00000400 h i/o (direct addressing area) i/o 00002000 h 00004000 h flash-cache (8 kbytes) 00001000 h dma 00006000 h 00007000 h flash memory control 00008000 h 0000b000 h boot rom (4 kbytes) 0000c000 h can 0000d000 h 0002a000 h d-ram (0 wait, 24 kbytes) 00030000 h id-ram (16 kbytes) 00034000 h 00040000 h flash memory (384 kbytes) 00150000 h 00180000 h external bus area 00500000 h external data bus ffffffff h note: access prohibited areas 00148000 h flash memory (32 kbytes) 00100000 h external bus area 00080000 h external bus area 000a0000 h
mb91460b series document number: 002-04608 rev. *a page 56 of 126 12. i/o map 12.1 mb91f467ba/466ba, mb91f465bb/464bb note: initial values of register bits are represented as follows: ? 1 ?: initial value ? 1 ? ? 0 ?: initial value ? 0 ? ? x ?: initial value ? undefined ? ? - ?: no physical regi ster at this location access is barred with an u ndefined data access attribute. address register block ? 0 ? 1 ? 2 ? 3 000000 h pdr0 [r/w] xxxxxxxx pdr1 [r/w] xxxxxxxx pdr2 [r/w] xxxxxxxx pdr3 [r/w] xxxxxxxx t-unit port data register read/write attribute register initial value after reset register name (column 1 register at a ddress 4n, column 2 register at address 4n + 1...) leftmost register address (for word access, the register in column 1 becomes the msb side of the data.)
mb91460b series document number: 002-04608 rev. *a page 57 of 126 address register block +0 +1 +2 +3 000000 h pdr00 [r/w] xxxxxxxx pdr01 [r/w] xxxxxxxx reserved reserved r-bus port data register 000004 h reserved pdr05 [r/w] - - xxxxxx pdr06 [r/w] xxxxxxxx pdr07 [r/w] xxxxxxxx 000008 h pdr08 [r/w] x - - x - - - x pdr09 [r/w] - - - - - - xx pdr10 [r/w] - - - - - - - x reserved 00000c h reserved reserved pdr14 [r/w] xxxxxxxx pdr15 [r/w] xxxxxxxx 000010 h pdr16 [r/w] xxxxxxxx pdr17 [r/w] xxxxxxxx pdr18 [r/w] - xxx - xxx pdr19 [r/w] - xxx - xxx 000014 h pdr20 [r/w] - xxx - xxx pdr21 [r/w] - - - - - - xx pdr22 [r/w] xxxxxxxx pdr23 [r/w] xxxxxxxx 000018 h pdr24 [r/w] xxxxxxxx reserved pdr26 [r/w] xxxxxxxx pdr27 [r/w] xxxxxxxx 00001c h pdr28 [r/w] xxxxxxxx pdr29 [r/w] xxxxxxxx reserved reserved 000020 h to 00002c h reserved 000030 h eirr0 [r/w] mb91f467ba: 00000000:md3=0 11110000:md3=1 mb91f465bb: xxxxxxxx enir0 [r/w] 00000000 elvr0 [r/w] 00000000 00000000 external interrupt (int 0 to int 7) 000034 h eirr1 [r/w] mb91f467ba: 00000000 mb91f465bb: xxxxxxxx enir1 [r/w] 00000000 elvr1 [r/w] 00000000 00000000 external interrupt (int 8 to int 15) 000038 h dicr [r/w] - - - - - - - 0 hrcl [r/w] 0 - - 11111 rbsync delay interrupt 00003c h reserved reserved 000040 h scr00 [r/w,w] 00000000 smr00 [r/w,w] 00000000 ssr00 [r/w,r] 00001000 rdr00/tdr00 [r/w] 00000000 lin-usart 0 000044 h escr00 [r/w] 00000x00 eccr00 [r/w,r,w] -00000xx reserved 000048 h 00004c h reserved reserved 000050 h scr02 [r/w,w] 00000000 smr02 [r/w,w] 00000000 ssr02 [r/w,r] 00001000 rdr02/tdr02 [r/w] 00000000 lin-usart 2 000054 h escr02 [r/w] 00000x00 eccr02 [r/w,r,w] -00000xx reserved
mb91460b series document number: 002-04608 rev. *a page 58 of 126 000058 h scr03 [r/w,w] 00000000 smr03 [r/w,w] 00000000 ssr03 [r/w,r] 00001000 rdr03/tdr03 [r/w] 00000000 lin-usart 3 00005c h escr03 [r/w] 00000x00 eccr03 [r/w,r,w] -00000xx reserved 000060 h scr04 [r/w,w] 00000000 smr04 [r/w,w] 00000000 ssr04 [r/w,r] 00001000 rdr04/tdr04 [r/w] 00000000 lin-usart 4 with fifo 000064 h escr04 [r/w] 00000x00 eccr04 [r/w,r,w] -00000xx fsr04 [r] - - - 00000 fcr04 [r/w] 0001 - 000 000068 h scr05 [r/w,w] 00000000 smr05 [r/w,w] 00000000 ssr05 [r/w,r] 00001000 rdr05/tdr05 [r/w] 00000000 lin-usart 5 with fifo 00006c h escr05 [r/w] 00000x00 eccr05 [r/w,r,w] -00000xx fsr05 [r] - - - 00000 fcr05 [r/w] 0001 - 000 000070 h scr06 [r/w,w] 00000000 smr06 [r/w,w] 00000000 ssr06 [r/w,r] 00001000 rdr06/tdr06 [r/w] 00000000 lin-usart 6 with fifo 000074 h escr06 [r/w] 00000x00 eccr06 [r/w,r,w] -00000xx fsr06 [r] - - - 00000 fcr06 [r/w] 0001 - 000 000078 h scr07 [r/w,w] 00000000 smr07 [r/w,w] 00000000 ssr07 [r/w,r] 00001000 rdr07/tdr07 [r/w] 00000000 lin-usart 7 with fifo 00007c h escr07 [r/w] 00000x00 eccr07 [r/w,r,w] -00000xx fsr07 [r] - - - 00000 fcr07 [r/w] 0001 - 000 000080 h bgr100 [r/w] 00000000 bgr000 [r/w] 00000000 reserved reserved baud rate generator lin-usart 0 to 7 000084 h bgr102 [r/w] 00000000 bgr002 [r/w] 00000000 bgr103 [r/w] 00000000 bgr003 [r/w] 00000000 000088 h bgr104 [r/w] 00000000 bgr004 [r/w] 00000000 bgr105 [r/w] 00000000 bgr005 [r/w] 00000000 00008c h bgr106 [r/w] 00000000 bgr006 [r/w] 00000000 bgr107 [r/w] 00000000 bgr007 [r/w] 00000000 000090 h to 0000cc h reserved reserved 0000d0 h ibcr0 [r/w] 00000000 ibsr0 [r] 00000000 itbah0 [r/w] - - - - - - 00 itbal0 [r/w] 00000000 i 2 c 0 0000d4 h itmkh0 [r/w] 00 - - - - 11 itmkl0 [r/w] 11111111 ismk0 [r/w] 01111111 isba0 [r/w] - 0000000 0000d8 h reserved idar0 [r/w] 00000000 iccr0 [r/w] - 0011111 reserved 0000dc h ibcr1 [r/w] 00000000 ibsr1 [r] 00000000 itbah1 [r/w] - - - - - - 00 itbal1 [r/w] 00000000 i 2 c 1 0000e0 h itmkh1 [r/w] 00 - - - - 11 itmkl1 [r/w] 11111111 ismk1 [r/w] 01111111 isba1 [r/w] - 0000000 0000e4 h reserved idar1 [r/w] 00000000 iccr1 [r/w] - 0011111 reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 59 of 126 0000e8 h to 0000fc h reserved reserved 000100 h gcn10 [r/w] 00110010 00010000 reserved gcn20 [r/w] - - - - 0000 ppg control 0 to 3 000104 h gcn11 [r/w] 00110010 00010000 reserved gcn21 [r/w] - - - - 0000 ppg control 4 to 7 000108 h gcn12 [r/w] 00110010 00010000 reserved gcn22 [r/w] - - - - 0000 ppg control 8 to 11 000110 h ptmr00 [r] 11111111 11111111 pcsr00 [w] xxxxxxxx xxxxxxxx ppg 0 000114 h pdut00 [w] xxxxxxxx xxxxxxxx pcnh00 [r/w] 0000000 - pcnl00 [r/w] 000000 - 0 000118 h ptmr01 [r] 11111111 11111111 pcsr01 [w] xxxxxxxx xxxxxxxx ppg 1 00011c h pdut01 [w] xxxxxxxx xxxxxxxx pcnh01 [r/w] 0000000 - pcnl01 [r/w] 000000 - 0 000120 h ptmr02 [r] 11111111 11111111 pcsr02 [w] xxxxxxxx xxxxxxxx ppg 2 000124 h pdut02 [w] xxxxxxxx xxxxxxxx pcnh02 [r/w] 0000000 - pcnl02 [r/w] 000000 - 0 000128 h ptmr03 [r] 11111111 11111111 pcsr03 [w] xxxxxxxx xxxxxxxx ppg 3 00012c h pdut03 [w] xxxxxxxx xxxxxxxx pcnh03 [r/w] 0000000 - pcnl03 [r/w] 000000 - 0 000130 h ptmr04 [r] 11111111 11111111 pcsr04 [w] xxxxxxxx xxxxxxxx ppg 4 000134 h pdut04 [w] xxxxxxxx xxxxxxxx pcnh04 [r/w] 0000000 - pcnl04 [r/w] 000000 - 0 000138 h ptmr05 [r] 11111111 11111111 pcsr05 [w] xxxxxxxx xxxxxxxx ppg 5 00013c h pdut05 [w] xxxxxxxx xxxxxxxx pcnh05 [r/w] 0000000 - pcnl05 [r/w] 000000 - 0 000140 h ptmr06 [r] 11111111 11111111 pcsr06 [w] xxxxxxxx xxxxxxxx ppg 6 000144 h pdut06 [w] xxxxxxxx xxxxxxxx pcnh06 [r/w] 0000000 - pcnl06 [r/w] 000000 - 0 000148 h ptmr07 [r] 11111111 11111111 pcsr07 [w] xxxxxxxx xxxxxxxx ppg 7 00014c h pdut07 [w] xxxxxxxx xxxxxxxx pcnh07 [r/w] 0000000 - pcnl07 [r/w] 000000 - 0 000150 h ptmr08 [r] 11111111 11111111 pcsr08 [w] xxxxxxxx xxxxxxxx ppg 8 000154 h pdut08 [w] xxxxxxxx xxxxxxxx pcnh08 [r/w] 0000000 - pcnl08 [r/w] 000000 - 0 address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 60 of 126 000158 h ptmr09 [r] 11111111 11111111 pcsr09 [w] xxxxxxxx xxxxxxxx ppg 9 00015c h pdut09 [w] xxxxxxxx xxxxxxxx pcnh09 [r/w] 0000000 - pcnl09 [r/w] 000000 - 0 000160 h ptmr10 [r] 11111111 11111111 pcsr10 [w] xxxxxxxx xxxxxxxx ppg 10 000164 h pdut10 [w] xxxxxxxx xxxxxxxx pcnh10 [r/w] 0000000 - pcnl10 [r/w] 000000 - 0 000168 h ptmr11 [r] 11111111 11111111 pcsr11 [w] xxxxxxxx xxxxxxxx ppg 11 00016c h pdut11 [w] xxxxxxxx xxxxxxxx pcnh11 [r/w] 0000000 - pcnl11 [r/w] 000000 - 0 000170 h to 00017c h reserved reserved 000180 h reserved ics01 [r/w] 00000000 reserved ics23 [r/w] 00000000 input capture 0 to 3 000184 h ipcp0 [r] xxxxxxxx xxxxxxxx ipcp1 [r] xxxxxxxx xxxxxxxx 000188 h ipcp2 [r] xxxxxxxx xxxxxxxx ipcp3 [r] xxxxxxxx xxxxxxxx 00018c h ocs01 [r/w] - - - 0 - - 00 0000 - - 00 ocs23 [r/w] - - - 0 - - 00 0000 - - 00 output compare 0 to 3 000190 h occp0 [r/w] xxxxxxxx xxxxxxxx occp1 [r/w] xxxxxxxx xxxxxxxx 000194 h occp2 [r/w] xxxxxxxx xxxxxxxx occp3 [r/w] xxxxxxxx xxxxxxxx 000198 h sgcrh [r/w] 0000 - - 00 sgcrl [r/w] - - 0 - - 000 sgfr [r/w, r] xxxxxxxx xxxxxxxx sound generator 00019c h sgar [r/w] 00000000 reserved sgtr [r/w] xxxxxxxx sgdr [r/w] xxxxxxxx 0001a0 h aderh [r/w] 00000000 00000000 aderl [r/w] 00000000 00000000 a/d converter 0001a4 adcs1 [r/w] 00000000 adcs0 [r/w] 00000000 adcr1 [r] 000000xx adcr0 [r] xxxxxxxx 0001a8 h adct1 [r/w] 00010000 adct0 [r/w] 00101100 adsch [r/w] - - - 00000 adech [r/w] - - - 00000 0001ac h reserved acsr0 [r/w] -11xxx00 reserved reserved alarm comparator 0 to 1 0001b0 h tmrlr0 [w] xxxxxxxx xxxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 (ppg 0, ppg 1) 0001b4 h reserved tmcsrh0 [r/w] - - - 00000 tmcsrl0 [r/w] 0 - 000000 0001b8 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 (ppg 2, ppg 3) 0001bc h reserved tmcsrh1 [r/w] - - - 00000 tmcsrl1 [r/w] 0 - 000000 address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 61 of 126 0001c0 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 (ppg 4, ppg 5) 0001c4 h reserved tmcsrh2 [r/w] - - - 00000 tmcsrl2 [r/w] 0 - 000000 0001c8 h tmrlr3 [w] xxxxxxxx xxxxxxxx tmr3 [r] xxxxxxxx xxxxxxxx reload timer 3 (ppg 6, ppg 7) 0001cc h reserved tmcsrh3 [r/w] - - - 00000 tmcsrl3 [r/w] 0 - 000000 0001d0 h tmrlr4 [w] xxxxxxxx xxxxxxxx tmr4 [r] xxxxxxxx xxxxxxxx reload timer 4 (ppg 8, ppg 9) 0001d4 h reserved tmcsrh4 [r/w] - - - 00000 tmcsrl4 [r/w] 0 - 000000 0001d8 h tmrlr5 [w] xxxxxxxx xxxxxxxx tmr5 [r] xxxxxxxx xxxxxxxx reload timer 5 (ppg 10, ppg 11) 0001dc h reserved tmcsrh5 [r/w] - - - 00000 tmcsrl5 [r/w] 0 - 000000 0001e0 h tmrlr6 [w] xxxxxxxx xxxxxxxx tmr6 [r] xxxxxxxx xxxxxxxx reload timer 6 (ppg 12, ppg 13) 0001e4 h reserved tmcsrh6 [r/w] - - - 00000 tmcsrl6 [r/w] 0 - 000000 0001e8 h tmrlr7 [w] xxxxxxxx xxxxxxxx tmr7 [r] xxxxxxxx xxxxxxxx reload timer 7 (ppg 14, ppg 15) (a/d converter) 0001ec h reserved tmcsrh7 [r/w] - - - 00000 tmcsrl7 [r/w] 0 - 000000 0001f0 h tcdt0 [r/w] xxxxxxxx xxxxxxxx reserved tccs0 [r/w] 00000000 free running timer 0 (icu 0, icu 1) 0001f4 h tcdt1 [r/w] xxxxxxxx xxxxxxxx reserved tccs1 [r/w] 00000000 free running timer 1 (icu 2, icu 3) 0001f8 h tcdt2 [r/w] xxxxxxxx xxxxxxxx reserved tccs2 [r/w] 00000000 free running timer 2 (ocu 0, ocu 1) 0001fc h tcdt3 [r/w] xxxxxxxx xxxxxxxx reserved tccs3 [r/w] 00000000 free running timer 3 (ocu 2, ocu 3) address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 62 of 126 000200 h dmaca0 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000208 h dmaca1 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000220 h dmaca4 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000224 h dmacb4 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000228 h to 00023c h reserved 000240 h dmacr [r/w] 00 - - 0000 reserved 000244 h to 0002cc h reserved reserved 0002d0 h reserved ics045 [r/w] 00000000 reserved ics67 [r/w] 00000000 input capture 4 to 7 0002d4 h ipcp4 [r] xxxxxxxx xxxxxxxx ipcp5 [r] xxxxxxxx xxxxxxxx 0002d8 h ipcp6 [r] xxxxxxxx xxxxxxxx ipcp7 [r] xxxxxxxx xxxxxxxx 0002dc h ocs45 [r/w] - - - 0 - - 00 0000 - - 00 ocs67 [r/w] - - - 0 - - 00 0000 - - 00 output compare 4 to 7 0002e0 h occp4 [r/w] xxxxxxxx xxxxxxxx occp5 [r/w] xxxxxxxx xxxxxxxx 0002e4 h occp6 [r/w] xxxxxxxx xxxxxxxx occp7 [r/w] xxxxxxxx xxxxxxxx 0002e8 h to 0002ec h reserved reserved 0002f0 h tcdt4 [r/w] xxxxxxxx xxxxxxxx reserved tccs4 [r/w] 00000000 free running timer 4 (icu 4, icu 5) 0002f4 h tcdt5 [r/w] xxxxxxxx xxxxxxxx reserved tccs5 [r/w] 00000000 free running timer 5 (icu 6, icu 7) 0002f8 h tcdt6 [r/w] xxxxxxxx xxxxxxxx reserved tccs6 [r/w] 00000000 free running timer 6 (ocu 4, ocu 5) 0002fc h tcdt7 [r/w] xxxxxxxx xxxxxxxx reserved tccs7 [r/w] 00000000 free running timer 7 (ocu 6, ocu 7) address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 63 of 126 000300 h udrc1 [w] 00000000 udrc0 [w] 00000000 udcr1 [r] 00000000 udcr0 [r] 00000000 up/down counter 0 to 1 000304 h udcch0 [r/w] 00000000 udccl0 [r/w] 00001000 reserved udcs0 [r/w] 00000000 000308 h udcch1 [r/w] 00000000 udccl1 [r/w] 00001000 reserved udcs1 [r/w] 00000000 00030c h to 00031c h reserved reserved 000320 h gcn13 [r/w] 00110010 00010000 reserved gcn23 [r/w] - - - - 0000 ppg control 12 to 15 000324 h to 00032c h reserved reserved 000330 h ptmr12 [r] 11111111 11111111 pcsr12 [w] xxxxxxxx xxxxxxxx ppg 12 000334 h pdut12 [w] xxxxxxxx xxxxxxxx pcnh12 [r/w] 0000000 - pcnl12 [r/w] 000000 - 0 000338 h ptmr13 [r] 11111111 11111111 pcsr13 [w] xxxxxxxx xxxxxxxx ppg 13 00033c h pdut13 [w] xxxxxxxx xxxxxxxx pcnh13 [r/w] 0000000 - pcnl13 [r/w] 000000 - 0 000340 h ptmr14 [r] 11111111 11111111 pcsr14 [w] xxxxxxxx xxxxxxxx ppg 14 000344 h pdut14 [w] xxxxxxxx xxxxxxxx pcnh14 [r/w] 0000000 - pcnl14 [r/w] 000000 - 0 000348 h ptmr15 [r] 11111111 11111111 pcsr15 [w] xxxxxxxx xxxxxxxx ppg 15 00034c h pdut15 [w] xxxxxxxx xxxxxxxx pcnh15 [r/w] 0000000 - pcnl15 [r/w] 000000 - 0 000350 h to 00038c h reserved reserved 000390 h roms [r] 11111111 00000000 (mb91f467ba/466ba) 11111111 01000011 (mb91f465bb/464bb) reserved rom select register 000394 h to 0003ec h reserved reserved 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h to 00043c h reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 64 of 126 000440 h icr00 [r/w] ---11111 icr01 [r/w] ---11111 icr02 [r/w] ---11111 icr03 [r/w] ---11111 interrupt controller 000444 h icr04 [r/w] ---11111 icr05 [r/w] ---11111 icr06 [r/w] ---11111 icr07 [r/w] ---11111 000448 h icr08 [r/w] ---11111 icr09 [r/w] ---11111 icr10 [r/w] ---11111 icr11 [r/w] ---11111 00044c h icr12 [r/w] ---11111 icr13 [r/w] ---11111 icr14 [r/w] ---11111 icr15 [r/w] ---11111 000450 h icr16 [r/w] ---11111 icr17 [r/w] ---11111 icr18 [r/w] ---11111 icr19 [r/w] ---11111 000454 h icr20 [r/w] ---11111 icr21 [r/w] ---11111 icr22 [r/w] ---11111 icr23 [r/w] ---11111 000458 h icr24 [r/w] ---11111 icr25 [r/w] ---11111 icr26 [r/w] ---11111 icr27 [r/w] ---11111 00045c h icr28 [r/w] ---11111 icr29 [r/w] ---11111 icr30 [r/w] ---11111 icr31 [r/w] ---11111 000460 h icr32 [r/w] ---11111 icr33 [r/w] ---11111 icr34[r/w] ---11111 icr35 [r/w] ---11111 000464 h icr36 [r/w] ---11111 icr37 [r/w] ---11111 icr38 [r/w] ---11111 icr39 [r/w] ---11111 000468 h icr40 [r/w] ---11111 icr41 [r/w] ---11111 icr42 [r/w] ---11111 icr43 [r/w] ---11111 00046c h icr44 [r/w] ---11111 icr45 [r/w] ---11111 icr46 [r/w] ---11111 icr47 [r/w] ---11111 000470 h icr48 [r/w] ---11111 icr49 [r/w] ---11111 icr50 [r/w] ---11111 icr51 [r/w] ---11111 000474 h icr52 [r/w] ---11111 icr53 [r/w] ---11111 icr54 [r/w] ---11111 icr55 [r/w] ---11111 000478 h icr56 [r/w] ---11111 icr57 [r/w] ---11111 icr58 [r/w] ---11111 icr59 [r/w] ---11111 00047c h icr60 [r/w] ---11111 icr61 [r/w] ---11111 icr62 [r/w] ---11111 icr63 [r/w] ---11111 interrupt controller 000480 h rsrr [r/w] 10000000 stcr [r/w] 00110011 tbcr [r/w] 00xxxx00 ctbr [w] xxxxxxxx clock control 000484 h clkr [r/w] - - - - 0000 wpr [w] xxxxxxxx divr0 [r/w] 00000011 divr1 [r/w] 00000000 000488 h reserved reserved 00048c h plldivm [r/w] - - - - 0000 plldivn [r/w] - - 000000 plldivg [r/w] - - - - 0000 pllmulg [r/w] 00000000 pll interface 000490 h pllctrl [r/w] - - - - 0000 reserved 000494 h oscc1 [r/w] - - - - - 010 oscs1 [r/w] 00001111 oscc2 [r/w] - - - - - 010 oscs2 [r/w] 00001111 main/sub oscillator control (reserved) 000498 h porten [r/w] - - - - - - 00 reserved port input enable control address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 65 of 126 0004a0 h reserved wtcer [r/w] - - - - - - 00 wtcr [r/w] 00000000 000 - 00 - 0 real time clock (watch timer) 0004a4 h reserved wtbr [r/w] - - - xxxxx xxxxxxxx xxxxxxxx 0004a8 h wthr [r/w] - - - 00000 wtmr [r/w] - - 000000 wtsr [r/w] - - 000000 reserved 0004ac h csvtr [r/w] - - - 00010 csvcr [r/w] - 011100 cscfg [r/w] 0x000000 cmcfg [r/w] 00000000 clock- supervisor / selector/ monitor 0004b0 h cucr [r/w] - - - - - - - - - - - 0 - - 00 cutd [r/w] 10000000 00000000 calibration of sub clock 0004b4 h cutr1 [r] - - - - - - - - 00000000 cutr2 [r] 00000000 00000000 0004b8 h cmpr [r/w] - - 000010 11111101 reserved cmcr [r/w] - 001 - - 00 clock modulator 0004bc h cmt1 [r/w] 00000000 1 - - - 0000 cmt2 [r/w] - - 000000 - - 000000 0004c0 h canpre [r/w] 0 - - - 0000 canckd [r/w] - - 000000 reserved can clock control 0004c4 h lvsel [r/w] 00000111 lvdet [r/w] 00000 - 00 hwwde [r/w] - - - - - - 00 hwwd [r/w,w] 00011000 low voltage detection/ hardware watchdog 0004c8 h oscrh [r/w] 000 - - 001 oscrl [r/w] - - - - - 000 wpcrh [r/w] 000 - - 001 wpcrl [r/w] - - - - - - 00 main-/sub-oscillation sta- bilisation timer 0004cc h osccr [r/w] - - - - - - 00 reserved regsel [r/w] - - 000110 regctr [r/w] - - - 0 - - 00 main- oscillation standby control / main/ sub regulator control 0004d0 h to 00063c h reserved reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 66 of 126 000640 h asr0 [r/w] 00000000 00000000 acr0 [r/w] 1111**00 00000000 [2] external bus unit 000644 h asr1 [r/w] xxxxxxxx xxxxxxxx acr1 [r/w] xxxxxxxx xxxxxxxx 000648 h asr2 [r/w] xxxxxxxx xxxxxxxx acr2 [r/w] xxxxxxxx xxxxxxxx 00064c h asr3 [r/w] xxxxxxxx xxxxxxxx acr3 [r/w] xxxxxxxx xxxxxxxx 000650 h asr4 [r/w] xxxxxxxx xxxxxxxx acr4 [r/w] xxxxxxxx xxxxxxxx 000654 h asr5 [r/w] xxxxxxxx xxxxxxxx acr5 [r/w] xxxxxxxx xxxxxxxx 000658 h asr6 [r/w] xxxxxxxx xxxxxxxx acr6 [r/w] xxxxxxxx xxxxxxxx 00065c h asr7 [r/w] xxxxxxxx xxxxxxxx acr7 [r/w] xxxxxxxx xxxxxxxx 000660 h awr0 [r/w] 01111111 11111*11 awr1 [r/w] xxxxxxxx xxxxxxxx 000664 h awr2 [r/w] xxxxxxxx xxxxxxxx awr3 [r/w] xxxxxxxx xxxxxxxx 000668 h awr4 [r/w] xxxxxxxx xxxxxxxx awr5 [r/w] xxxxxxxx xxxxxxxx 00066c h awr6 [r/w] xxxxxxxx xxxxxxxx awr7 [r/w] xxxxxxxx xxxxxxxx 000670 h mcra [r/w] xxxxxxxx mcrb [r/w] xxxxxxxx reserved 000674 h reserved 000678 h iowr0 [r/w] xxxxxxxx iowr1 [r/w] xxxxxxxx iowr2 [r/w] xxxxxxxx iowr3 [r/w] xxxxxxxx 00067c h reserved 000680 h cser [r/w] 00000001 cher [r/w] 11111111 reserved tcr [r/w] 0000**** [3] 000684 h rcrh [r/w] 00xxxxxx rcrl [r/w] xxxx0xxx reserved 000688 h to 0007f8 h reserved external bus unit 0007fc h reserved modr [w] xxxxxxxx reserved mode register 000800 h to 000cfc h reserved reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 67 of 126 000d00 h pdrd00 [r] xxxxxxxx pdrd01 [r] xxxxxxxx reserved r-bus port data direct read register 000d04 h reserved pdrd05 [r] - - xxxxxx pdrd06 [r] xxxxxxxx pdrd07 [r] xxxxxxxx 000d08 h pdrd08 [r] x - - x - - -x pdrd09 [r] - - - - - - xx pdrd10 [r] - - - - - - - x reserved 000d0c h reserved pdrd14 [r] xxxxxxxx pdrd15 [r] xxxxxxxx 000d10 h pdrd16 [r] xxxxxxxx pdrd17 [r] xxxxxxxx pdrd18 [r] - xxx - xxx pdrd19 [r] - xxx - xxx 000d14 h pdrd20 [r] - xxx - xxx pdrd21 [r] - - - - - - - x pdrd22 [r] xxxxxxxx pdrd23 [r] xxxxxxxx 000d18 h pdrd24 [r] xxxxxxxx reserved pdrd26 [r] xxxxxxxx pdrd27 [r] xxxxxxxx 000d1c h pdrd28 [r] xxxxxxxx pdrd29 [r] xxxxxxxx reserved 000d20 h to 000d3c h reserved 000d40 h ddr00 [r/w] 00000000 ddr01 [r/w] 00000000 reserved r-bus port direction register 000d44 h reserved ddr05 [r/w] - - 000000 ddr06 [r/w] 00000000 ddr07 [r/w] 00000000 000d48 h ddr08 [r/w] 0 - - 0 - - -0 ddr09 [r/w] - - - - - - 00 ddr10 [r/w] - - - - - - -0 reserved 000d4c h reserved ddr14 [r/w] 00000000 ddr15 [r/w] 00000000 000d50 h ddr16 [r/w] 00000000 ddr17 [r/w] 00000000 ddr18 [r/w] - 000 - 000 ddr19 [r/w] - 000 - 000 000d54 h ddr20 [r/w] - 000 - 000 ddr21 [r/w] - - - - - - 00 ddr22 [r/w] 00000000 ddr23 [r/w] 00000000 000d58 h ddr24 [r/w] 00000000 reserved ddr26 [r/w] 00000000 ddr27 [r/w] 00000000 000d5c h ddr28 [r/w] 00000000 ddr29 [r/w] 00000000 reserved 000d60 h to 000d7c h reserved reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 68 of 126 000d80 h pfr00 [r/w] 11111111 pfr01 [r/w] 11111111 reserved r-bus port function register 000d84 h reserved pfr05 [r/w] - - 111111 pfr06 [r/w] 11111111 pfr07 [r/w] 11111111 000d88 h pfr08 [r/w] 1 - - 1 - - 11 pfr09 [r/w] - - - - - - 11 pfr10 [r/w] - - - - - - -1 reserved 000d8c h reserved pfr14 [r/w] 00000000 pfr15 [r/w] 00000000 000d90 h pfr16 [r/w] 00000000 pfr17 [r/w] 00000000 pfr18 [r/w] - 000 - 000 pfr19 [r/w] - 000 - 000 000d94 h pfr20 [r/w] - 000 - 000 pfr21 [r/w] - - - - - - 00 pfr22 [r/w] 0000-0-0 pfr23 [r/w] -0000000 000d98 h pfr24 [r/w] 00000000 reserved pfr26 [r/w] 00000000 pfr27 [r/w] 00000000 000d9c h pfr28 [r/w] 00000000 pfr29 [r/w] 00000000 reserved 000da0 h to 000dc4 h reserved 000dc8 h reserved epfr10 [r/w] - - - - - - - 0 reserved r-bus port extra function register 000dcc h reserved epfr14 [r/w] 00000000 epfr15 [r/w] 00000000 000dd0 h epfr16 [r/w] 0 - 00 - - - - reserved epfr18 [r/w] - 000 - 000 epfr19 [r/w] - 0- - - 0- - 000dd4 h epfr20 [r/w] - 000 - 000 epfr21 [r/w] - - - - - - - - reserved 000dd8 h reserved epfr26 [r/w] 00000000 epfr27 [r/w] 00000000 000ddc h to 000dfc h reserved reserved 000e00 h podr00 [r/w] 00000000 podr01 [r/w] 00000000 reserved r-bus port output drive select register 000e04 h reserved podr05 [r/w] - - 000000 podr06 [r/w] 00000000 podr07 [r/w] 00000000 000e08 h podr08 [r/w] 0 - - 0 - - - 0 podr09 [r/w] - - - - - - 00 podr10 [r/w] - - - - - - - 0 reserved 000e0c h reserved podr14 [r/w] 00000000 podr15 [r/w] 00000000 000e10 h podr16 [r/w] 00000000 podr17 [r/w] 00000000 podr18 [r/w] - 000 - 000 podr19 [r/w] - 000 - 000 000e14 h podr20 [r/w] - 000 - 000 podr21 [r/w] - - - - - - 00 podr22 [r/w] 00000000 podr23 [r/w] 00000000 000e18 h podr24 [r/w] 00000000 reserved podr26 [r/w] 00000000 podr27 [r/w] 00000000 000e1c h podr28 [r/w] 00000000 podr29 [r/w] 00000000 reserved 000e20 h to 000e3c h reserved reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 69 of 126 000e40 h pilr00 [r/w] 00000000 pilr01 [r/w] 00000000 reserved r-bus port input level select register 000e44 h reserved pilr05 [r/w] - - 000000 pilr06 [r/w] 00000000 pilr07 [r/w] 00000000 000e48 h pilr08 [r/w] 0 - - 0 - - - 0 pilr09 [r/w] - - - - - - 00 pilr10 [r/w] - - - - - - - 0 reserved 000e4c h reserved pilr14 [r/w] 00000000 pilr15 [r/w] 00000000 000e50 h pilr16 [r/w] 00000000 pilr17 [r/w] 00000000 pilr18 [r/w] - - - - - 000 pilr19 [r/w] - 000 - 000 000e54 h pilr20 [r/w] - 000 - 000 pilr21 [r/w] - - - - - - 00 pilr22 [r/w] 00000000 pilr23 [r/w] 00000000 000e58 h pilr24 [r/w] 00000000 reserved pilr26 [r/w] 00000000 pilr27 [r/w] 00000000 000e5c h pilr28 [r/w] 00000000 pilr29 [r/w] 00000000 reserved 000e60 h to 000e7c h reserved reserved 000e80 h epilr00 [r/w] 00000000 epilr01 [r/w] 00000000 reserved r-bus port extra input level select register 000e84 h reserved epilr05 [r/w] - - 000000 epilr06 [r/w] 00000000 epilr07 [r/w] 00000000 000e88 h epilr08 [r/w] 0 - - 0- - - 0 epilr09 [r/w] - - - - - - 00 epilr10 [r/w] - - - - - - - 0 reserved 000e8c h reserved epilr14 [r/w] 00000000 epilr15 [r/w] 00000000 000e90 h epilr16 [r/w] 00000000 epilr17 [r/w] 00000000 epilr18 [r/w] - - - - - 000 epilr19 [r/w] - 000 - 000 000e94 h epilr20 [r/w] - 000 - 000 epilr21 [r/w] - - - - - - 00 epilr22 [r/w] 00000000 epilr23 [r/w] 00000000 000e98 h epilr24 [r/w] 00000000 reserved epilr26 [r/w] 00000000 epilr27 [r/w] 00000000 000e9c h epilr28 [r/w] 00000000 epilr29 [r/w] 00000000 reserved 000ea0 h to 000ebc h reserved reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 70 of 126 000ec0 h pper00 [r/w] 00000000 pper01 [r/w] 00000000 reserved r-bus port pull-up/down enable register 000ec4 h reserved pper05 [r/w] - - 000000 pper06 [r/w] 00000000 pper07 [r/w] 00000000 000ec8 h pper08 [r/w] 0 - - 0 - - - 0 pper09 [r/w] - - - - - - 00 pper10 [r/w] - - - - - - - 0 reserved 000ecc h reserved pper14 [r/w] 00000000 pper15 [r/w] 00000000 000ed0 h pper16 [r/w] 00000000 pper17 [r/w] 00000000 pper18 [r/w] - 000 - 000 pper19 [r/w] - 000 - 000 000ed4 h pper20 [r/w] - 000 - 000 pper21 [r/w] - - - - - - 00 pper22 [r/w] 00000000 pper23 [r/w] 00000000 000ed8 h pper24 [r/w] 00000000 reserved pper26 [r/w] 00000000 pper27 [r/w] 00000000 000edc h pper28 [r/w] 00000000 pper29 [r/w] 00000000 reserved 000ee0 h to 000efc h reserved reserved 000f00 h ppcr00 [r/w] 11111111 ppcr01 [r/w] 11111111 reserved r-bus port pull-up/down control register 000f04 h reserved ppcr05 [r/w] - - 111111 ppcr06 [r/w] 11111111 ppcr07 [r/w] 11111111 000f08 h ppcr08 [r/w] 1 - - 1 - - - 1 ppcr09 [r/w] - - - - - - 11 ppcr10 [r/w] - - - - - - - 1 reserved 000f0c h reserved ppcr14 [r/w] 00000000 ppcr15 [r/w] 11111111 000f10 h ppcr16 [r/w] 00000000 ppcr17 [r/w] 00000000 ppcr18 [r/w] - 111- 111 ppcr19 [r/w] - 111- 111 000f14 h ppcr20 [r/w] - 111- 111 ppcr21 [r/w] - - - - - - 11 ppcr22 [r/w] 11111111 ppcr23 [r/w] 11111111 000f18 h ppcr24 [r/w] 11111111 reserved ppcr26 [r/w] 11111111 ppcr27 [r/w] 11111111 000f1c h ppcr28 [r/w] 11111111 ppcr29 [r/w] 11111111 reserved 000f20 h to 000f3c h reserved reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 71 of 126 001000 h dmasa0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001018 h dmasa3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00101c h dmada3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001020 h dmasa4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001028 h to 003ffc h reserved reserved 002000 h to 006ffc h flash-cache size is 8 kbytes : 004000 h to 005ffc h flash-cache / i-ram area 007000 h fmcs [r/w] 01101000 fmcr [r/w] - - - - 0000 fchcr [r/w] - - - - - - 00 10000011 flash memory/ i-cache control register 007004 h fmwt [r/w] 11111111 11111111 reserved fmps [r/w] - - - - - 000 007008 h fmac [r] 00000000 00000000 00000000 00000000 00700c h fcha0 [r/w] - - - - - - - - - - 000000 00000000 00000000 i-cache non-cacheable area setting register 007010 h fcha1 [r/w] - - - - - - - - - - 000000 00000000 00000000 007014 h to 007ffc h reserved reserved 008000 h to 00bffc h boot-rom size is 4 kbytes : 00b000 h to 00bffc h (instruction access is 1 wait cycle, data ac cess is 1 wait cycle) boot rom area 00c000 h ctrlr0 [r/w] 00000000 00000001 statr0 [r/w] 00000000 00000000 can 0 control register 00c004 h errcnt0 [r] 00000000 00000000 btr0 [r/w] 00100011 00000001 00c008 h intr0 [r] 00000000 00000000 testr0 [r/w] 00000000 x0000000 00c00c h brpe0 [r/w] 00000000 00000000 cbsync0 address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 72 of 126 00c010 h if1creq0 [r/w] 00000000 00000001 if1cmsk0 [r/w] 00000000 00000000 can 0 if 1 register 00c014 h if1msk20 [r/w] 11111111 11111111 if1msk10 [r/w] 11111111 11111111 00c018 h if1arb20 [r/w] 00000000 00000000 if1arb10 [r/w] 00000000 00000000 00c01c h if1mctr0 [r/w] 00000000 00000000 reserved 00c020 h if1dta10 [r/w] 00000000 00000000 if1dta20 [r/w] 00000000 00000000 00c024 h if1dtb10 [r/w] 00000000 00000000 if1dtb20 [r/w] 00000000 00000000 00c028 h to 00c02c h reserved 00c030 h if1dta20 [r/w] 00000000 00000000 if1dta10 [r/w] 00000000 00000000 00c034 h if1dtb20 [r/w] 00000000 00000000 if1dtb10 [r/w] 00000000 00000000 00c038 h to 00c03c h reserved 00c040 h if2creq0 [r/w] 00000000 00000001 if2cmsk0 [r/w] 00000000 00000000 can 0 if 2 register 00c044 h if2msk20 [r/w] 11111111 11111111 if2msk10 [r/w] 11111111 11111111 00c048 h if2arb20 [r/w] 00000000 00000000 if2arb10 [r/w] 00000000 00000000 00c04c h if2mctr0 [r/w] 00000000 00000000 reserved 00c050 h if2dta10 [r/w] 00000000 00000000 if2dta20 [r/w] 00000000 00000000 00c054 h if2dtb10 [r/w] 00000000 00000000 if2dtb20 [r/w] 00000000 00000000 00c058 h to 00c05c h reserved 00c060 h if2dta20 [r/w] 00000000 00000000 if2dta10 [r/w] 00000000 00000000 00c064 h if2dtb20 [r/w] 00000000 00000000 if2dtb10 [r/w] 00000000 00000000 00c068 h to 00c07c h reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 73 of 126 00c080 h treqr20 [r] 00000000 00000000 treqr10 [r] 00000000 00000000 can 0 status flags 00c084 h to 00c08c h reserved reserved 00c090 h newdt20 [r] 00000000 00000000 newdt10 [r] 00000000 00000000 00c094 h to 00c09c h reserved reserved 00c0a0 h intpnd20 [r] 00000000 00000000 intpnd10 [r] 00000000 00000000 00c0a4 h to 00c0ac h reserved reserved 00c0b0 h msgval20 [r] 00000000 00000000 msgval10 [r] 00000000 00000000 00c0b4 h to 00c0fc h reserved reserved 00c100 h ctrlr1 [r/w] 00000000 00000001 statr1 [r/w] 00000000 00000000 can 1 control register 00c104 h errcnt1 [r] 00000000 00000000 btr1 [r/w] 00100011 00000001 00c108 h intr1 [r] 00000000 00000000 testr1 [r/w] 00000000 x0000000 00c10c h brpe1 [r/w] 00000000 00000000 cbsync1 00c110 h if1creq1 [r/w] 00000000 00000001 if1cmsk1 [r/w] 00000000 00000000 can 1 if 1 register 00c114 h if1msk21 [r/w] 11111111 11111111 if1msk11 [r/w] 11111111 11111111 00c118 h if1arb21 [r/w] 00000000 00000000 if1arb11 [r/w] 00000000 00000000 00c11c h if1mctr1 [r/w] 00000000 00000000 reserved 00c120 h if1dta11 [r/w] 00000000 00000000 if1dta21 [r/w] 00000000 00000000 00c124 h if1dtb11 [r/w] 00000000 00000000 if1dtb21 [r/w] 00000000 00000000 00c128 h to 00c12c h reserved 00c130 h if1dta21 [r/w] 00000000 00000000 if1dta11 [r/w] 00000000 00000000 00c134 h if1dtb21 [r/w] 00000000 00000000 if1dtb11 [r/w] 00000000 00000000 00c138 h to 00c13c h reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 74 of 126 00c140 h if2creq1 [r/w] 00000000 00000001 if2cmsk1 [r/w] 00000000 00000000 can 1 if 2 register 00c144 h if2msk21 [r/w] 11111111 11111111 if2msk11 [r/w] 11111111 11111111 00c148 h if2arb21 [r/w] 00000000 00000000 if2arb11 [r/w] 00000000 00000000 00c14c h if2mctr1 [r/w] 00000000 00000000 reserved 00c150 h if2dta11 [r/w] 00000000 00000000 if2dta21 [r/w] 00000000 00000000 00c154 h if2dtb11 [r/w] 00000000 00000000 if2dtb21 [r/w] 00000000 00000000 00c158 h to 00c15c h reserved 00c160 h if2dta21 [r/w] 00000000 00000000 if2dta11 [r/w] 00000000 00000000 00c164 h if2dtb21 [r/w] 00000000 00000000 if2dtb11 [r/w] 00000000 00000000 00c168 h to 00c17c h reserved 00c180 h treqr21 [r] 00000000 00000000 treqr11 [r] 00000000 00000000 can 1 status flags 00c184 h to 00c18c h reserved reserved 00c190 h newdt21 [r] 00000000 00000000 newdt11 [r] 00000000 00000000 00c194 h to 00c19c h reserved reserved 00c1a0 h intpnd21 [r] 00000000 00000000 intpnd11 [r] 00000000 00000000 00c1a4 h to 00c1ac h reserved reserved 00c1b0 h msgval21 [r] 00000000 00000000 msgval11 [r] 00000000 00000000 00c1b4 h to 00c1fc h reserved reserved 00c200 h ctrlr2 [r/w] 00000000 00000001 statr2 [r/w] 00000000 00000000 can 2 control register 00c204 h errcnt2 [r] 00000000 00000000 btr2 [r/w] 00100011 00000001 00c208 h intr2 [r] 00000000 00000000 testr2 [r/w] 00000000 x0000000 00c20c h brpe2 [r/w] 00000000 00000000 cbsync2 address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 75 of 126 00c210 h if1creq2 [r/w] 00000000 00000001 if1cmsk2 [r/w] 00000000 00000000 can 2 if 1 register 00c214 h if1msk22 [r/w] 11111111 11111111 if1msk12 [r/w] 11111111 11111111 00c218 h if1arb22 [r/w] 00000000 00000000 if1arb12 [r/w] 00000000 00000000 00c21c h if1mctr2 [r/w] 00000000 00000000 reserved 00c220 h if1dta12 [r/w] 00000000 00000000 if1dta22 [r/w] 00000000 00000000 00c224 h if1dtb12 [r/w] 00000000 00000000 if1dtb22 [r/w] 00000000 00000000 00c228 h to 00c22c h reserved 00c230 h if1dta22 [r/w] 00000000 00000000 if1dta12 [r/w] 00000000 00000000 00c234 h if1dtb22 [r/w] 00000000 00000000 if1dtb12 [r/w] 00000000 00000000 00c238 h to 00c23c h reserved 00c240 h if2creq2 [r/w] 00000000 00000001 if2cmsk2 [r/w] 00000000 00000000 can 2 if 2 register 00c244 h if2msk22 [r/w] 11111111 11111111 if2msk12 [r/w] 11111111 11111111 00c248 h if2arb22 [r/w] 00000000 00000000 if2arb12 [r/w] 00000000 00000000 00c24c h if2mctr2 [r/w] 00000000 00000000 reserved 00c250 h if2dta12 [r/w] 00000000 00000000 if2dta22 [r/w] 00000000 00000000 00c254 h if2dtb12 [r/w] 00000000 00000000 if2dtb22 [r/w] 00000000 00000000 00c258 h to 00c25c h reserved 00c260 h if2dta22 [r/w] 00000000 00000000 if2dta12 [r/w] 00000000 00000000 00c264 h if2dtb22 [r/w] 00000000 00000000 if2dtb12 [r/w] 00000000 00000000 00c268 h to 00c27c h reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 76 of 126 00c280 h treqr22 [r] 00000000 00000000 treqr12 [r] 00000000 00000000 can 2 status flags 00c284 h to 00c28c h reserved reserved 00c290 h newdt22 [r] 00000000 00000000 newdt12 [r] 00000000 00000000 00c294 h to 00c29c h reserved reserved 00c2a0 h intpnd22 [r] 00000000 00000000 intpnd12 [r] 00000000 00000000 00c2a4 h to 00c2ac h reserved reserved 00c2b0 h msgval22 [r] 00000000 00000000 msgval12 [r] 00000000 00000000 00c2b4 h to 00c2fc h reserved reserved 00c300 h ctrlr3 [r/w] 00000000 00000001 statr3 [r/w] 00000000 00000000 can 3 control register note: not on mb91f465bb/mb91f464 bb 00c304 h errcnt3 [r] 00000000 00000000 btr3 [r/w] 00100011 00000001 00c308 h intr3 [r] 00000000 00000000 testr3 [r/w] 00000000 x0000000 00c30c h brpe3 [r/w] 00000000 00000000 cbsync3 address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 77 of 126 address register block +0 +1 +2 +3 00c310 h if1creq3 [r/w] 00000000 00000001 if1cmsk3 [r/w] 00000000 00000000 can 3 if 1 register note : not on mb91f465bb/mb91f464 bb 00c314 h if1msk23 [r/w] 11111111 11111111 if1msk13 [r/w] 11111111 11111111 00c318 h if1arb23 [r/w] 00000000 00000000 if1arb13 [r/w] 00000000 00000000 00c31c h if1mctr3 [r/w] 00000000 00000000 reserved 00c320 h if1dta13 [r/w] 00000000 00000000 if1dta23 [r/w] 00000000 00000000 00c324 h if1dtb13 [r/w] 00000000 00000000 if1dtb23 [r/w] 00000000 00000000 00c328 h to 00c32c h reserved 00c330 h if1dta23 [r/w] 00000000 00000000 if1dta13 [r/w] 00000000 00000000 00c334 h if1dtb23 [r/w] 00000000 00000000 if1dtb13 [r/w] 00000000 00000000 00c338 h to 00c33c h reserved 00c340 h if2creq3 [r/w] 00000000 00000001 if2cmsk3 [r/w] 00000000 00000000 can 3 if 2 register note: not on mb91f465bb/mb91f464 bb 00c344 h if2msk23 [r/w] 11111111 11111111 if2msk13 [r/w] 11111111 11111111 00c348 h if2arb23 [r/w] 00000000 00000000 if2arb13 [r/w] 00000000 00000000 00c34c h if2mctr3 [r/w] 00000000 00000000 reserved 00c350 h if2dta13 [r/w] 00000000 00000000 if2dta23 [r/w] 00000000 00000000 00c354 h if2dtb13 [r/w] 00000000 00000000 if2dtb23 [r/w] 00000000 00000000 00c358 h to 00c35c h reserved 00c360 h if2dta23 [r/w] 00000000 00000000 if2dta13 [r/w] 00000000 00000000 00c364 h if2dtb23 [r/w] 00000000 00000000 if2dtb13 [r/w] 00000000 00000000 00c368 h to 00c37c h reserved
mb91460b series document number: 002-04608 rev. *a page 78 of 126 00c380 h treqr23 [r] 00000000 00000000 treqr13 [r] 00000000 00000000 can 3 status flags note : not on mb91f465bb/mb91f464 bb 00c384 h to 00c38c h reserved 00c390 h newdt23 [r] 00000000 00000000 newdt13 [r] 00000000 00000000 00c394 h to 00c39c h reserved 00c3a0 h intpnd23 [r] 00000000 00000000 intpnd13 [r] 00000000 00000000 00c3a4 h to 00c3ac h reserved 00c3b0 h msgval23 [r] 00000000 00000000 msgval13 [r] 00000000 00000000 00c3b4 h to 00c3fc h reserved 00c400 h ctrlr4 [r/w] 00000000 00000001 statr4 [r/w] 00000000 00000000 can 4 control register note : not on mb91f465bb/mb91f464 bb 00c404 h errcnt4 [r] 00000000 00000000 btr4 [r/w] 00100011 00000001 00c408 h intr4 [r] 00000000 00000000 testr4 [r/w] 00000000 x0000000 00c40c h brpe4 [r/w] 00000000 00000000 cbsync4 00c410 h if1creq4 [r/w] 00000000 00000001 if1cmsk4 [r/w] 00000000 00000000 can 4 if 1 register note: not on mb91f465bb/mb91f464 bb 00c414 h if1msk24 [r/w] 11111111 11111111 if1msk14 [r/w] 11111111 11111111 00c418 h if1arb24 [r/w] 00000000 00000000 if1arb14 [r/w] 00000000 00000000 00c41c h if1mctr4 [r/w] 00000000 00000000 reserved 00c420 h if1dta14 [r/w] 00000000 00000000 if1dta24 [r/w] 00000000 00000000 00c424 h if1dtb14 [r/w] 00000000 00000000 if1dtb24 [r/w] 00000000 00000000 00c428 h to 00c42c h reserved 00c430 h if1dta24 [r/w] 00000000 00000000 if1dta14 [r/w] 00000000 00000000 00c434 h if1dtb24 [r/w] 00000000 00000000 if1dtb14 [r/w] 00000000 00000000 00c438 h to 00c43c h reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 79 of 126 00c440 h if2creq4 [r/w] 00000000 00000001 if2cmsk4 [r/w] 00000000 00000000 can 4 if 2 register note: not on mb91f465bb/mb91f464 bb 00c444 h if2msk24 [r/w] 11111111 11111111 if2msk14 [r/w] 11111111 11111111 00c448 h if2arb24 [r/w] 00000000 00000000 if2arb14 [r/w] 00000000 00000000 00c44c h if2mctr4 [r/w] 00000000 00000000 reserved 00c450 h if2dta14 [r/w] 00000000 00000000 if2dta24 [r/w] 00000000 00000000 00c454 h if2dtb14 [r/w] 00000000 00000000 if2dtb24 [r/w] 00000000 00000000 00c458 h to 00c45c h reserved 00c460 h if2dta24 [r/w] 00000000 00000000 if2dta14 [r/w] 00000000 00000000 00c464 h if2dtb24 [r/w] 00000000 00000000 if2dtb14 [r/w] 00000000 00000000 00c468 h to 00c47c h reserved 00c480 h treqr24 [r] 00000000 00000000 treqr14 [r] 00000000 00000000 can 4 status flags note: not on mb91f465bb/mb91f464 bb 00c484 h to 00c48c h reserved 00c490 h newdt24 [r] 00000000 00000000 newdt14 [r] 00000000 00000000 00c494 h to 00c49c h reserved 00c4a0 h intpnd24 [r] 00000000 00000000 intpnd14 [r] 00000000 00000000 00c4a4 h to 00c4ac h reserved 00c4b0 h msgval24 [r] 00000000 00000000 msgval14 [r] 00000000 00000000 00c4b4 h to 00c4fc h reserved 00c500 h ctrlr5 [r/w] 00000000 00000001 statr5 [r/w] 00000000 00000000 can 5 control register note: not on mb91f465bb/mb91f464 bb 00c504 h errcnt5 [r] 00000000 00000000 btr5 [r/w] 00100011 00000001 00c508 h intr5 [r] 00000000 00000000 testr5 [r/w] 00000000 x0000000 00c50c h brpe5 [r/w] 00000000 00000000 cbsync5 address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 80 of 126 00c510 h if1creq5 [r/w] 00000000 00000001 if1cmsk5 [r/w] 00000000 00000000 can 5 if 1 register note: not on mb91f465bb/mb91f464 bb 00c514 h if1msk25 [r/w] 11111111 11111111 if1msk15 [r/w] 11111111 11111111 00c518 h if1arb25 [r/w] 00000000 00000000 if1arb15 [r/w] 00000000 00000000 00c51c h if1mctr5 [r/w] 00000000 00000000 reserved 00c520 h if1dta15 [r/w] 00000000 00000000 if1dta25 [r/w] 00000000 00000000 00c524 h if1dtb15 [r/w] 00000000 00000000 if1dtb25 [r/w] 00000000 00000000 00c528 h to 00c52c h reserved 00c530 h if1dta25 [r/w] 00000000 00000000 if1dta15 [r/w] 00000000 00000000 00c534 h if1dtb25 [r/w] 00000000 00000000 if1dtb15 [r/w] 00000000 00000000 00c538 h to 00c53c h reserved 00c540 h if2creq5 [r/w] 00000000 00000001 if2cmsk5 [r/w] 00000000 00000000 can 5 if 2 register note : not on mb91f465bb/mb91f464 bb 00c544 h if2msk25 [r/w] 11111111 11111111 if2msk15 [r/w] 11111111 11111111 00c548 h if2arb25 [r/w] 00000000 00000000 if2arb15 [r/w] 00000000 00000000 00c54c h if2mctr5 [r/w] 00000000 00000000 reserved 00c550 h if2dta15 [r/w] 00000000 00000000 if2dta25 [r/w] 00000000 00000000 00c554 h if2dtb15 [r/w] 00000000 00000000 if2dtb25 [r/w] 00000000 00000000 00c558 h to 00c55c h reserved 00c560 h if2dta25 [r/w] 00000000 00000000 if2dta15 [r/w] 00000000 00000000 00c564 h if2dtb25 [r/w] 00000000 00000000 if2dtb15 [r/w] 00000000 00000000 00c568 h to 00c57c h reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 81 of 126 00c580 h treqr25 [r] 00000000 00000000 treqr15 [r] 00000000 00000000 can 5 status flags note: not on mb91f465bb/mb91f464 bb 00c584 h to 00c58c h reserved 00c590 h newdt25 [r] 00000000 00000000 newdt15 [r] 00000000 00000000 00c594 h to 00c59c h reserved 00c5a0 h intpnd25 [r] 00000000 00000000 intpnd15 [r] 00000000 00000000 00c5a4 h to 00c5ac h reserved 00c5b0 h msgval25 [r] 00000000 00000000 msgval15 [r] 00000000 00000000 00c5b4 h to 00effc h reserved 00f000 h bctrl [r/w] - - - - - - - - - - - - - - - - 11111100 00000000 edsu / mpu 00f004 h bstat [r/w] - - - - - - - - - - - - - 000 00000000 10 - - 000000 00f008 h biac [r] - - - - - - - - - - - - - - - - 00000000 00000000 00f00c h boac [r] - - - - - - - - - - - - - - - - 00000000 00000000 00f010 h birq [r/w] - - - - - - - - - - - - - - - - 00000000 00000000 00f014 h to 00f01c h reserved 00f020 h bcr0 [r/w] - - - - - - - - 00000000 00000000 00000000 00f024 h bcr1 [r/w] - - - - - - - - 00000000 00000000 00000000 00f028 h bcr2 [r/w] - - - - - - - - 00000000 00000000 00000000 00f02c h bcr3 [r/w] - - - - - - - - 00000000 00000000 00000000 00f030 h to 00f07c h reserved reserved address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 82 of 126 1. depends on the number of available can channels 2. acr0 [11 : 10] depends on mode vector fetch information on bus width 3. tcr [3 : 0] init value = 0000, keeps value after rst 00f080 h bad0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx edsu / mpu 00f084 h bad1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f088 h bad2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f08c h bad3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f090 h bad4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f094 h bad5 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f098 h bad6 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f09c h bad7 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0a0 h bad8 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0a4 h bad9 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0a8 h bad10 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0ac h bad11 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0b0 h bad12 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0b4 h bad13 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0b8 h bad14 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0bc h bad15 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0c0 h to 01fffc h reserved edsu / mpu 020000 h to 02fffc h d-ram size is 24 kbytes : 02a000 h - 02fffc h (data access is 0 wait cycles) d-ram area 030000 h to 03fffc h id-ram size is 16 kbytes : 030000 h - 033ffc h (instruction access is 0 wait cycle s, data access is 1 wait cycle) id-ram area address register block +0 +1 +2 +3
mb91460b series document number: 002-04608 rev. *a page 83 of 126 12.2 flash memory and external bus area 12.2.1 mb91f467ba/466ba 64bit read dat[63:0] 32bit read/write dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 040000 h to 05fff8 h sa8 (64kb) sa9 (64kb) roms0 060000 h to 07fff8 h sa10 (64kb) sa11 (64kb) roms1 080000 h to 09fff8 h sa12 (64kb) sa13 (64kb) roms2 0a0000 h to 0bfff8 h sa14 (64kb) sa15 (64kb) roms3 0c0000 h to 0dfff8 h sa16 (64kb) sa17 (64kb) roms4 0e0000 h to 0ffff0 h sa18 (64kb) sa19 (64kb) roms5 0ffff8 h fmv [r] 06 00 00 00 h frv [r] 00 00 bf f8 h 100000 h to 11fff8 h sa20 (64kb, mb91f467ba) reserved (mb91f466ba) sa21 (64kb, mb91f467ba) reserved (mb91f466ba) roms6 120000 h to 13fff8 h sa22 (64kb, mb91f467ba) reserved (mb91f466ba) sa23 (64kb, mb91f467b) reserved (mb91f466ba) 140000 h to 143ff8 h sa0 (8kb) sa1 (8kb) roms7 144000 h to 17ff8 h sa2 (8kb) sa3 (8kb) 148000 h to 14bff8 h sa4 (8kb) sa5 (8kb) 14c000 h to 14fff8 h sa6 (8kb) sa7 (8kb) 150000 h to17fff8 h reserved
mb91460b series document number: 002-04608 rev. *a page 84 of 126 notes : write operations to address 0ffff8 h and 0ffffc h are not possible. when reading these addresses, the values shown above will be read. 64bit read dat[63:0] 32bit read/write dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 180000 h to 1bfff8 h external bus area roms8 1c0000 h to 1ffff8 h roms9 200000 h to 27fff8 h roms10 280000 h to 2ffff8 h roms11 300000 h to 37fff8 h roms12 380000 h to 3ffff8 h roms13 400000 h to 47fff8 h roms14 480000 h to 4ffff8 h roms15
mb91460b series document number: 002-04608 rev. *a page 85 of 126 12.2.2 mb91f465bb/464bb 32bit read dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 040000 h to 05fff8 h reserved reserved roms0 060000 h to 07fff8 h reserved reserved roms1 080000 h to 09fff8 h sa12 (64kb) reserved (mb91f464bb) sa13 (64kb) reserved (mb91f464bb) roms2 0a0000 h to 0bfff8 h sa14 (64kb) sa15 (64kb) roms3 0c0000 h to 0dfff8 h sa16 (64kb) sa17 (64kb) roms4 0e0000 h to 0ffff0 h sa18 (64kb) sa19 (64kb) roms5 0ffff8 h fmv [r] 06 00 00 00 h frv [r] 00 00 bf f8 h 100000 h to 11fff8 h external bus area roms6 120000 h to 13fff8 h 140000 h to 143ff8 h external bus area roms7 144000 h to 17ff8 h 148000 h to 14bff8 h sa4 (8kb) sa5 (8kb) 14c000 h to 14fff8 h sa6 (8kb) sa7 (8kb) 150000 h to17fff8 h reserved
mb91460b series document number: 002-04608 rev. *a page 86 of 126 notes : write operations to address 0ffff8 h and 0ffffc h are not possible. when reading these addresses, the values shown above will be read. on mb91f465bb/f464bb, write acce ss to the flash is only possible in 16-bit mode. 32bit read/write dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 180000 h to 1bfff8 h external bus area roms8 1c0000 h to 1ffff8 h roms9 200000 h to 27fff8 h roms10 280000 h to 2ffff8 h roms11 300000 h to 37fff8 h roms12 380000 h to 3ffff8 h roms13 400000 h to 47fff8 h roms14 480000 h to 4ffff8 h roms15
mb91460b series document number: 002-04608 rev. *a page 87 of 126 13. interrupt vector table interrupt interrupt number interrupt level [1] interrupt vector [2] dma resource number decimal hexa- decimal setting register register address offset default vector address reset 0 00 ? ? 3fc h 000ffffc h ? mode vector 1 01 ? ? 3f8 h 000ffff8 h ? system reserved 2 02 ? ? 3f4 h 000ffff4 h ? system reserved 3 03 ? ? 3f0 h 000ffff0 h ? system reserved 4 04 ? ? 3ec h 000fffec h ? cpu supervisor mode (int #5 instruction) [5] 505 ? ?3e8 h 000fffe8 h ? memory protection exception [5] 606 ? ?3e4 h 000fffe4 h ? system reserved 7 07 ? ? 3e0 h 000fffe0 h ? system reserved 8 08 ? ? 3dc h 000fffdc h ? system reserved 9 09 ? ? 3d8 h 000fffd8 h ? system reserved 10 0a ? ? 3d4 h 000fffd4 h ? system reserved 11 0b ? ? 3d0 h 000fffd0 h ? system reserved 12 0c ? ? 3cc h 000fffcc h ? system reserved 13 0d ? ? 3c8 h 000fffc8 h ? undefined instruction exception 14 0e ? ? 3c4 h 000fffc4 h ? nmi request 15 0f f h fixed 3c0 h 000fffc0 h ? external interrupt 0 16 10 icr00 440 h 3bc h 000fffbc h 0, 16 external interrupt 1 17 11 3b8 h 000fffb8 h 1, 17 external interrupt 2 18 12 icr01 441 h 3b4 h 000fffb4 h 2, 18 external interrupt 3 19 13 3b0 h 000fffb0 h 3, 19 external interrupt 4 20 14 icr02 442 h 3ac h 000fffac h 20 external interrupt 5 21 15 3a8 h 000fffa8 h 21 external interrupt 6 22 16 icr03 443 h 3a4 h 000fffa4 h 22 external interrupt 7 23 17 3a0 h 000fffa0 h 23 external interrupt 8 24 18 icr04 444 h 39c h 000fff9c h ? external interrupt 9 25 19 398 h 000fff98 h ? external interrupt 10 26 1a icr05 445 h 394 h 000fff94 h ? external interrupt 11 27 1b 390 h 000fff90 h ? external interrupt 12 28 1c icr06 446 h 38c h 000fff8c h ? external interrupt 13 29 1d 388 h 000fff88 h ? external interrupt 14 30 1e icr07 447 h 384 h 000fff84 h ? external interrupt 15 31 1f 380 h 000fff80 h ? reload timer 0 32 20 icr08 448 h 37c h 000fff7c h 4, 32 reload timer 1 33 21 378 h 000fff78 h 5, 33 reload timer 2 34 22 icr09 449 h 374 h 000fff74 h 34 reload timer 3 35 23 370 h 000fff70 h 35
mb91460b series document number: 002-04608 rev. *a page 88 of 126 reload timer 4 36 24 icr10 44a h 36c h 000fff6c h 36 reload timer 5 37 25 368 h 000fff68 h 37 reload timer 6 38 26 icr11 44b h 364 h 000fff64 h 38 reload timer 7 39 27 360 h 000fff60 h 39 free run timer 0 40 28 icr12 44c h 35c h 000fff5c h 40 free run timer 1 41 29 358 h 000fff58 h 41 free run timer 2 42 2a icr13 44d h 354 h 000fff54 h 42 free run timer 3 43 2b 350 h 000fff50 h 43 free run timer 4 44 2c icr14 44e h 34c h 000fff4c h 44 free run timer 5 45 2d 348 h 000fff48 h 45 free run timer 6 46 2e icr15 44f h 344 h 000fff44 h 46 free run timer 7 47 2f 340 h 000fff40 h 47 can 0 48 30 icr16 450 h 33c h 000fff3c h ? can 1 49 31 338 h 000fff38 h ? can 2 50 32 icr17 451 h 334 h 000fff34 h ? can 3 not on mb91f465bb/464bb 51 33 330 h 000fff30 h ? can 4 not on mb91f465bb/464bb 52 34 icr18 452 h 32c h 000fff2c h ? can 5 not on mb91f465bb/464bb 53 35 328 h 000fff28 h ? lin-usart 0 rx 54 36 icr19 453 h 324 h 000fff24 h 6, 48 lin-usart 0 tx 55 37 320 h 000fff20 h 7, 49 reserved 56 38 icr20 454 h 31c h 000fff1c h 8, 50 reserved 57 39 318 h 000fff18 h 9, 51 lin-usart 2 rx 58 3a icr21 455 h 314 h 000fff14 h 52 lin-usart 2 tx 59 3b 310 h 000fff10 h 53 lin-usart 3 rx 60 3c icr22 456 h 30c h 000fff0c h 54 lin-usart 3 tx 61 3d 308 h 000fff08 h 55 system reserved 62 3e icr23 *3 457 h 304 h 000fff04 h ? delayed interrupt 63 3f 300 h 000fff00 h ? system reserved [4] 64 40 icr24 458 h 2fc h 000ffefc h ? system reserved [4] 65 41 2f8 h 000ffef8 h ? lin-usart (fifo) 4 rx 66 42 icr25 459 h 2f4 h 000ffef4 h 10, 56 lin-usart (fifo) 4 tx 67 43 2f0 h 000ffef0 h 11, 57 lin-usart (fifo) 5 rx 68 44 icr26 45a h 2ec h 000ffeec h 12, 58 lin-usart (fifo) 5 tx 69 45 2e8 h 000ffee8 h 13, 59 lin-usart (fifo) 6 rx 70 46 icr27 45b h 2e4 h 000ffee4 h 60 lin-usart (fifo) 6 tx 71 47 2e0 h 000ffee0 h 61 lin-usart (fifo) 7 rx 72 48 icr28 45c h 2dc h 000ffedc h 62 lin-usart (fifo) 7 tx 73 49 2d8 h 000ffed8 h 63 interrupt interrupt number interrupt level [1] interrupt vector [2] dma resource number decimal hexa- decimal setting register register address offset default vector address
mb91460b series document number: 002-04608 rev. *a page 89 of 126 i 2 c 0 74 4a icr29 45d h 2d4 h 000ffed4 h ? i 2 c 1 75 4b 2d0 h 000ffed0 h ? reserved 76 4c icr30 45e h 2cc h 000ffecc h 64 reserved 77 4d 2c8 h 000ffec8 h 65 reserved 78 4e icr31 45f h 2c4 h 000ffec4 h 66 reserved 79 4f 2c0 h 000ffec0 h 67 reserved 80 50 icr32 460 h 2bc h 000ffebc h 68 reserved 81 51 2b8 h 000ffeb8 h 69 reserved 82 52 icr33 461 h 2b4 h 000ffeb4 h 70 reserved 83 53 2b0 h 000ffeb0 h 71 reserved 84 54 icr34 462 h 2ac h 000ffeac h 72 reserved 85 55 2a8 h 000ffea8 h 73 reserved 86 56 icr35 463 h 2a4 h 000ffea4 h 74 reserved 87 57 2a0 h 000ffea0 h 75 reserved 88 58 icr36 464 h 29c h 000ffe9c h 76 reserved 89 59 298 h 000ffe98 h 77 reserved 90 5a icr37 465 h 294 h 000ffe94 h 78 reserved 91 5b 290 h 000ffe90 h 79 input capture 0 92 5c icr38 466 h 28c h 000ffe8c h 80 input capture 1 93 5d 288 h 000ffe88 h 81 input capture 2 94 5e icr39 467 h 284 h 000ffe84 h 82 input capture 3 95 5f 280 h 000ffe80 h 83 input capture 4 96 60 icr40 468 h 27c h 000ffe7c h 84 input capture 5 97 61 278 h 000ffe78 h 85 input capture 6 98 62 icr41 469 h 274 h 000ffe74 h 86 input capture 7 99 63 270 h 000ffe70 h 87 output compare 0 100 64 icr42 46a h 26c h 000ffe6c h 88 output compare 1 101 65 268 h 000ffe68 h 89 output compare 2 102 66 icr43 46b h 264 h 000ffe64 h 90 output compare 3 103 67 260 h 000ffe60 h 91 output compare 4 104 68 icr44 46c h 25c h 000ffe5c h 92 output compare 5 105 69 258 h 000ffe58 h 93 output compare 6 106 6a icr45 46d h 254 h 000ffe54 h 94 output compare 7 107 6b 250 h 000ffe50 h 95 sound generator 108 6c icr46 46e h 24c h 000ffe4c h ? reserved 109 6d 248 h 000ffe48 h ? system reserved 110 6e icr47 [3] 46f h 244 h 000ffe44 h ? system reserved 111 6f 240 h 000ffe40 h ? ppg 0 112 70 icr48 470 h 23c h 000ffe3c h 15, 96 ppg 1 113 71 238 h 000ffe38 h 97 interrupt interrupt number interrupt level [1] interrupt vector [2] dma resource number decimal hexa- decimal setting register register address offset default vector address
mb91460b series document number: 002-04608 rev. *a page 90 of 126 1. the interrupt control registers (icrs) are located in the interrupt controller and set the interrupt level for each interrup t request. an icr is provided for each interrupt request. 2. the vector address for each eit (exception, interrupt or trap ) is calculated by adding the listed offset to the table base r egister value (tbr) . the tbr specifies the top of the eit vector table. the addresse s listed in the table are for the default tbr value (000ffc00 h ) . the tbr is initialized to this value by a reset. the tbr is set to 000ffc00 h after the internal boot rom is executed. 3. icr23 and icr47 can be exchanged by setting the realos compatibility bit (addr 0c03 h : ios[0]) 4. used by realos 5. memory protection unit (mpu) support ppg 2 114 72 icr49 471 h 234 h 000ffe34 h 98 ppg 3 115 73 230 h 000ffe30 h 99 ppg 4 116 74 icr50 472 h 22c h 000ffe2c h 100 ppg 5 117 75 228 h 000ffe28 h 101 ppg 6 118 76 icr51 473 h 224 h 000ffe24 h 102 ppg 7 119 77 220 h 000ffe20 h 103 ppg 8 120 78 icr52 474 h 21c h 000ffe1c h 104 ppg 9 121 79 218 h 000ffe18 h 105 ppg 10 122 7a icr53 475 h 214 h 000ffe14 h 106 ppg 11 123 7b 210 h 000ffe10 h 107 ppg 12 124 7c icr54 476 h 20c h 000ffe0c h 108 ppg 13 125 7d 208 h 000ffe08 h 109 ppg 14 126 7e icr55 477 h 204 h 000ffe04 h 110 ppg 15 127 7f 200 h 000ffe00 h 111 up/down counter 0 128 80 icr56 478 h 1fc h 000ffdfc h ? up/down counter 1 129 81 1f8 h 000ffdf8 h ? reserved 130 82 icr57 479 h 1f4 h 000ffdf4 h ? reserved 131 83 1f0 h 000ffdf0 h ? real time clock 132 84 icr58 47a h 1ec h 000ffdec h ? calibration unit 133 85 1e8 h 000ffde8 h ? a/d converter 0 134 86 icr59 47b h 1e4 h 000ffde4 h 14, 112 system reserved 135 87 1e0 h 000ffde0 h ? alarm comparator 0 136 88 icr60 47c h 1dc h 000ffddc h ? reserved 137 89 1d8 h 000ffdd8 h ? low voltage detection 138 8a icr61 47d h 1d4 h 000ffdd4 h ? reserved 139 8b 1d0 h 000ffdd0 h ? time base overflow 140 8c icr62 47e h 1cc h 000ffdcc h ? pll clock gear 141 8d 1c8 h 000ffdc8 h ? dma controller 142 8e icr63 47f h 1c4 h 000ffdc4 h ? main/sub osc stability wait 143 8f 1c0 h 000ffdc0 h ? security vector 144 90 ? ? 1bc h 000ffdbc h ? used by the int instruction. 145 to 255 91 to ff ?? 1b8 h to 000 h 000ffdb8 h to 000ffc00 h ? interrupt interrupt number interrupt level [1] interrupt vector [2] dma resource number decimal hexa- decimal setting register register address offset default vector address
mb91460b series document number: 002-04608 rev. *a page 91 of 126 14. recommended settings 14.1 pll and clock gear settings please note that for mb91f467ba/466ba and mb91f465bb/464bb the co re base clock frequencies are valid in the 1.8v operation mode of the main regulator and flash. table 7. recommended pll divider and clock gear settings pll input (clk) [mhz] frequency parameter clockgear parameter pll output (x) [mhz] core base clock [mhz] remarks divm divn divg mulg mulg 4 2 25 16 24 200 100 not on mb91f467ba/46 6ba 4 2 24 16 24 192 96 4 2 23 16 24 184 92 4 2 22 16 24 176 88 4 2 21 16 20 168 84 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 88 44 4 4 10 16 24 160 40 4 4 9 16 24 144 36 4 4 8 16 24 128 32 4 4 7 16 24 112 28 4 6 6 16 24 144 24 4 8 5 16 28 160 20 4 10 4 16 32 160 16 4 12 3 16 32 144 12
mb91460b series document number: 002-04608 rev. *a page 92 of 126 14.2 clock modulator settings the following table shows all possible settings for the clock modulator in a base clock frequency range from 32mhz up to 88mhz. the flash access time settings need to be adjusted according to fm ax while the pll and clockgear settings should be set accordi ng to base clock frequency. table 8. clock modulator settings, frequency range and supported supply voltage modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz] 1 3 026f 88 79.5 98.5 not on mb91f467ba/466ba 1 3 026f 84 76.1 93.8 1 3 026f 80 72.6 89.1 1 5 02ae 80 68.7 95.8 2 3 046e 80 68.7 95.8 1 3 026f 76 69.1 84.5 1 5 02ae 76 65.3 90.8 1 7 02ed 76 62 98.1 not on mb91f467ba/466ba 2 3 046e 76 65.3 90.8 3 3 066d 76 62 98.1 not on mb91f467ba/466ba 1 3 026f 72 65.5 79.9 1 5 02ae 72 62 85.8 1 7 02ed 72 58.8 92.7 2 3 046e 72 62 85.8 3 3 066d 72 58.8 92.7 1 3 026f 68 62 75.3 1 5 02ae 68 58.7 80.9 1 7 02ed 68 55.7 87.3 1 9 032c 68 53 95 2 3 046e 68 58.7 80.9 2 5 04ac 68 53 95 3 3 066d 68 55.7 87.3 4 3 086c 68 53 95 1 3 026f 64 58.5 70.7 1 5 02ae 64 55.3 75.9 1 7 02ed 64 52.5 82 1 9 032c 64 49.9 89.1 1 11 036b 64 47.6 97.6 not on mb91f467ba/466ba 2 3 046e 64 55.3 75.9 2 5 04ac 64 49.9 89.1 3 3 066d 64 52.5 82 4 3 086c 64 49.9 89.1
mb91460b series document number: 002-04608 rev. *a page 93 of 126 5 3 0a6b 64 47.6 97.6 not on mb91f467ba/466ba 1 3 026f 60 54.9 66.1 1 5 02ae 60 51.9 71 1 7 02ed 60 49.3 76.7 1 9 032c 60 46.9 83.3 1 11 036b 60 44.7 91.3 2 3 046e 60 51.9 71 2 5 04ac 60 46.9 83.3 3 3 066d 60 49.3 76.7 4 3 086c 60 46.9 83.3 5 3 0a6b 60 44.7 91.3 1 3 026f 56 51.4 61.6 1 5 02ae 56 48.6 66.1 1 7 02ed 56 46.1 71.4 1 9 032c 56 43.8 77.6 1 11 036b 56 41.8 84.9 1 13 03aa 56 39.9 93.8 2 3 046e 56 48.6 66.1 2 5 04ac 56 43.8 77.6 2 7 04ea 56 39.9 93.8 3 3 066d 56 46.1 71.4 3 5 06aa 56 39.9 93.8 4 3 086c 56 43.8 77.6 5 3 0a6b 56 41.8 84.9 6 3 0c6a 56 39.9 93.8 1 3 026f 52 47.8 57 1 5 02ae 52 45.2 61.2 1 7 02ed 52 42.9 66.1 1 9 032c 52 40.8 71.8 1 11 036b 52 38.8 78.6 1 13 03aa 52 37.1 86.8 1 15 03e9 52 35.5 96.9 not on mb91f467ba/466ba 2 3 046e 52 45.2 61.2 2 5 04ac 52 40.8 71.8 2 7 04ea 52 37.1 86.8 3 3 066d 52 42.9 66.1 3 5 06aa 52 37.1 86.8 4 3 086c 52 40.8 71.8 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
mb91460b series document number: 002-04608 rev. *a page 94 of 126 5 3 0a6b 52 38.8 78.6 6 3 0c6a 52 37.1 86.8 7 3 0e69 52 35.5 96.9 not on mb91f467ba/466ba 1 3 026f 48 44.2 52.5 1 5 02ae 48 41.8 56.4 1 7 02ed 48 39.6 60.9 1 9 032c 48 37.7 66.1 1 11 036b 48 35.9 72.3 1 13 03aa 48 34.3 79.9 1 15 03e9 48 32.8 89.1 2 3 046e 48 41.8 56.4 2 5 04ac 48 37.7 66.1 2 7 04ea 48 34.3 79.9 3 3 066d 48 39.6 60.9 3 5 06aa 48 34.3 79.9 4 3 086c 48 37.7 66.1 5 3 0a6b 48 35.9 72.3 6 3 0c6a 48 34.3 79.9 7 3 0e69 48 32.8 89.1 1 3 026f 44 40.6 48.1 1 5 02ae 44 38.4 51.6 1 7 02ed 44 36.4 55.7 1 9 032c 44 34.6 60.4 1 11 036b 44 33 66.1 1 13 03aa 44 31.5 73 1 15 03e9 44 30.1 81.4 2 3 046e 44 38.4 51.6 2 5 04ac 44 34.6 60.4 2 7 04ea 44 31.5 73 2 9 0528 44 28.9 92.1 3 3 066d 44 36.4 55.7 3 5 06aa 44 31.5 73 4 3 086c 44 34.6 60.4 4 5 08a8 44 28.9 92.1 5 3 0a6b 44 33 66.1 6 3 0c6a 44 31.5 73 7 3 0e69 44 30.1 81.4 8 3 1068 44 28.9 92.1 1 3 026f 40 37 43.6 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
mb91460b series document number: 002-04608 rev. *a page 95 of 126 1 5 02ae 40 34.9 46.8 1 7 02ed 40 33.1 50.5 1 9 032c 40 31.5 54.8 1 11 036b 40 30 59.9 1 13 03aa 40 28.7 66.1 1 15 03e9 40 27.4 73.7 2 3 046e 40 34.9 46.8 2 5 04ac 40 31.5 54.8 2 7 04ea 40 28.7 66.1 2 9 0528 40 26.3 83.3 3 3 066d 40 33.1 50.5 3 5 06aa 40 28.7 66.1 3 7 06e7 40 25.3 95.8 4 3 086c 40 31.5 54.8 4 5 08a8 40 26.3 83.3 5 3 0a6b 40 30 59.9 6 3 0c6a 40 28.7 66.1 7 3 0e69 40 27.4 73.7 8 3 1068 40 26.3 83.3 9 3 1267 40 25.3 95.8 1 3 026f 36 33.3 39.2 1 5 02ae 36 31.5 42 1 7 02ed 36 29.9 45.3 1 9 032c 36 28.4 49.2 1 11 036b 36 27.1 53.8 1 13 03aa 36 25.8 59.3 1 15 03e9 36 24.7 66.1 2 3 046e 36 31.5 42 2 5 04ac 36 28.4 49.2 2 7 04ea 36 25.8 59.3 2 9 0528 36 23.7 74.7 3 3 066d 36 29.9 45.3 3 5 06aa 36 25.8 59.3 3 7 06e7 36 22.8 85.8 4 3 086c 36 28.4 49.2 4 5 08a8 36 23.7 74.7 5 3 0a6b 36 27.1 53.8 6 3 0c6a 36 25.8 59.3 7 3 0e69 36 24.7 66.1 8 3 1068 36 23.7 74.7 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
mb91460b series document number: 002-04608 rev. *a page 96 of 126 9 3 1267 36 22.8 85.8 1 3 026f 32 29.7 34.7 1 5 02ae 32 28 37.3 1 7 02ed 32 26.6 40.2 1 9 032c 32 25.3 43.6 1 11 036b 32 24.1 47.7 1 13 03aa 32 23 52.5 1 15 03e9 32 22 58.6 2 3 046e 32 28 37.3 2 5 04ac 32 25.3 43.6 2 7 04ea 32 23 52.5 2 9 0528 32 21.1 66.1 2 11 0566 32 19.5 89.1 3 3 066d 32 26.6 40.2 3 5 06aa 32 23 52.5 3 7 06e7 32 20.3 75.9 4 3 086c 32 25.3 43.6 4 5 08a8 32 21.1 66.1 5 3 0a6b 32 24.1 47.7 5 5 0aa6 32 19.5 89.1 6 3 0c6a 32 23 52.5 7 3 0e69 32 22 58.6 8 3 1068 32 21.1 66.1 9 3 1267 32 20.3 75.9 10 3 1466 32 19.5 89.1 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
mb91460b series document number: 002-04608 rev. *a page 97 of 126 15. electrical characteristics 15.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply slew rate ?? 50 v/ms power supply voltage 1 [1] v dd 5r ? 0.3 ? 6.0 v power supply voltage 2 [1] v dd 5 ? 0.3 ? 6.0 v relationship of the supply voltages av cc 5 v dd 5-0.3 v dd 35-0.3 v dd 5+0.3 v dd 35+0.3 v at least one pin of the ports 26 to 29 (ann) is used as digital input or output. v ss 5-0.3 v dd 35-0.3 v dd 5+0.3 v dd 35+0.3 v all pins of the ports 26 to 29 (ann) follow the condition of v ia analog power supply voltage [1] av cc 5 ? 0.3 ? 6.0 v [2] analog reference power supply voltage [1] avrh ? 0.3 ? 6.0 v [2] input voltage 1 [1] v i1 vss5 ? 0.3 v dd 5 ? 0.3 v analog pin input voltage [1] v ia avss5 ? 0.3 avcc5 ? 0.3 v output voltage 1 [1] v o1 vss5 ? 0.3 v dd 5 ? 0.3 v maximum clamp current i clamp ? 4.0 ? 4.0 ma [3] total maximum clamp current ??? i clamp ?? 20 ma [3] ?l? level maximum output current [4] i ol ? 10 ma ?l? level average output current [5] i olav ? 8ma ?l? level total maximum output current ? i ol ? 100 ma ?l? level total average output current [6] ? i olav ? 50 ma ?h? level maximum output current [4] i oh ? ? 10 ma ?h? level average output current [5] i ohav ? ? 4ma ?h? level total maximum output current ? i oh ? ? 100 ma ?h? level total average output current [6] ? i ohav ? ? 25 ma permitted operating frequency mb91f465bb/f464bb f max, clkb ? 100 mhz t a 105 c f max, clkp ? 50 f max, clkt ? 50 f max, clkcan ? 50 permitted operating frequency mb91f465bb/f464bb f max, clkb ? 96 mhz t a 125 c f max, clkp ? 48 f max, clkt ? 48 f max, clkcan ? 48 permitted operating frequency mb91f467ba/f466ba f max, clkb ? 96 mhz t a 105 c f max, clkp ? 48 f max, clkt ? 48 f max, clkcan ? 48
mb91460b series document number: 002-04608 rev. *a page 98 of 126 1. the parameter is based on v ss 5 ? av ss 5 ? 0.0 v. 2. av cc 5 and avrh5 must not exceed v dd 5 ? 0.3 v. 3. use within recommended operating conditions. use with dc voltage (current). ? b signals are input signals that exceed the v dd 5 voltage. ? b signals should always be applied by c onnecting a limiting resistor between the ? b signal and the microcontroller. the value of the limiting resistor should be set so that the cu rrent input to the microcontroller pin does not exceed the rated value at any time, either instantaneously or for an extended period, when the ? b signal is input. note that when the microcontroller drive current is lo w, such as in the low power consumption modes, the ? b input potential can increase the potential at the power supply pin via a protective diode, possibly affe cting other devices. note that if the ? b signal is input when the microcontroller is off (not fixed at 0 v), power is suppli ed through the +b input pin; therefore, th e microcontroller may partially operate. note that if the ? b signal is input at power-on, since the pow er is supplied through the pin, the power-on reset may not function in the power su pply voltage. do not leave ? b input pins open. figure 2. example of recommended circuit : permitted operating frequency mb91f467ba/f466ba f max, clkb ? 92 mhz t a 125 c f max, clkp ? 46 f max, clkt ? 46 f max, clkcan ? 46 permitted power dissipation [7] p d ? 1200 *8 mw t a 85 c ? 600 *8 mw t a 105 c ? 1300 *8 mw t a 105 c, no flash program/erase [9] ? 1000 *8 mw t a 115 c, no flash program/erase [9] ? 750 *8 mw t a 125 c, no flash program/erase [9] operating temperature t a ? 40 ? 125 ? c storage temperature tstg ? 55 ? 150 ? c parameter symbol rating unit remarks min max p-ch n-ch v cc r input/output equivalent circuit ? b input (0 v to 16 v) limiting resistor protective diode
mb91460b series document number: 002-04608 rev. *a page 99 of 126 4. maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. 5. average output current is defined as the value of the aver age current flowing through any one of the corresponding pins for a 100 ms period. 6. total average output current is defined as the value of the average current flowing through al l of the corresponding pins fo r a 100 ms period. 7. the maximum permitted power dissipation depends onm the ambient temperature, the ai r flow velocity and the thermal conductan ce of the package on the pcb. the actual power dissipation depends on the cust omer application and can be calculated as follows: p d = p io + p int p io = ?? (v ol * i ol + v oh + i oh ) (io load power dissipation, su m is performed on all io ports) p int = v dd 5r * i cc + av cc 5 * i a + avrh5 * i r (internal power dissipation) 8. worst case value for the qfp package mounted on a 4-layer pcb at specified t a without air flow. 9. please contact fujitsu for reliability limitations when using under these conditions. warning: semiconductor devices can be permanently damaged by applic ation of stress (voltage, cu rrent, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings.
mb91460b series document number: 002-04608 rev. *a page 100 of 126 15.2 recommended operating conditions (v ss 5 ? av ss 5 ? 0.0 v) warning: the recommended operating conditions ar e required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics ar e warranted when the device is operated within these ranges. always use semiconductor devi ces within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditi ons, or combinations not re presented on the data sheet. users considering application outside the listed conditions are advised to contact thei r representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v dd 5 3.0 - 5.5 v v dd 5r 3.0 - 5.5 v internal regulator av cc 5 3.0 - 5.5 v a/d converter smoothing capacitor at vcc18c pin c s -4.7-mf use a x7r ceramic capacitor or a capacitor that has similar frequency characteristics. power supply slew rate - - 50 v/ms operating temperature t a - 40 - + 125 c main oscillation stabilisation time 10 ms lock-up time pll (4 mhz ->16 ...100mhz) 0.6 ms esd protection (human body model) v surge 2kv r discharge = 1.5kw c discharge = 100pf rc oscillator f rc100khz f rc2mhz 50 1 100 2 200 4 khz mhz vdd core 1.65v c s avss5 vss5 vcc18c
mb91460b series document number: 002-04608 rev. *a page 101 of 126 15.3 dc characteristics (v dd 5 ? av cc 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c ) parameter symbol pin name condition value unit remarks min typ max input ?h? voltage v ih - port inputs if cmos hysteresis 0.8/0.2 input is selected 0.8 v dd -v dd + 0.3 v cmos hysteresis input - port inputs if cmos hysteresis 0.7/0.3 input is selected 0.7 v dd -v dd + 0.3 v 4.5 v ? v dd ? 5.5 v 0.74 v dd -v dd + 0.3 v 3 v ? v dd < 4.5 v - automotive hysteresis input is se- lected 0.8 v dd -v dd + 0.3 v - port inputs if ttl input is selected 2.0 - v dd + 0.3 v v ihr initx - 0.8 v dd -v dd + 0.3 v initx input pin (cmos hysteresis) v ihm md_3 to md_0 - v dd - 0.3 - v dd + 0.3 v mode input pins v ihx0s x0, x0a - 2.5 - v dd + 0.3 v external clock in ?oscillation mode? v ihx0f x0 - 0.8 v dd -v dd + 0.3 v external clock in ?fast clock input mode? input ?l? voltage v il - port inputs if cmos hysteresis 0.8/0.2 input is selected v ss - 0.3 - 0.2 v dd v - port inputs if cmos hysteresis 0.7/0.3 input is selected v ss - 0.3 - 0.3 v dd v - port inputs if automotive hysteresis input is selected v ss - 0.3 - 0.5 v dd v 4.5 v v dd 5.5 v v ss - 0.3 - 0.46 v dd v3 v v dd < 4.5 v - port inputs if ttl input is selected v ss - 0.3 - 0.8 v v ilr initx - v ss - 0.3 - 0.2 v dd v initx input pin (cmos hysteresis) v ilm md_3 to md_0 - v ss - 0.3 - v ss + 0.3 v mode input pins v ilxds x0, x0a - v ss - 0.3 - 0.5 v external clock in ?oscillation mode?
mb91460b series document number: 002-04608 rev. *a page 102 of 126 parameter symbol pin name condition value unit remarks min typ max input ?l? voltage v ilxdf x0 - v ss - 0.3 - 0.2 v dd v external clock in ?fast clock input mode? output ?h? voltage v oh2 normal outputs 4.5v v dd 5.5v, i oh = - 2ma v dd - 0.5 - - v driving strength set to 2 ma 3.0v v dd 4.5v, i oh = - 1.6ma v oh5 normal outputs 4.5v v dd 5.5v, i oh = - 5ma v dd - 0.5 - - v driving strength set to 5 ma 3.0v v dd 4.5v, i oh = - 3ma v oh3 i 2 c outputs 3.0v v dd 5.5v, i oh = - 3ma v dd - 0.5 - - v output ?l? volt- age v ol2 normal outputs 4.5v v dd 5.5v, i oh = + 2ma --0.4v driving strength set to 2 ma 3.0v v dd 4.5v, i oh = + 1.6ma v ol5 normal outputs 4.5v v dd 5.5v, i oh = + 5ma --0.4v driving strength set to 5 ma 3.0v v dd 4.5v, i oh = + 3ma v ol3 i 2 c outputs 3.0v v dd 5.5v, i oh = + 3ma --0.4v input leakage current i il pnn_m [1] 3.0v v dd 5.5v v ss 5 < v i < v dd t a =25 c - 1 - + 1 ma 3.0v v dd 5.5v v ss 5 < v i < v dd t a =125 c - 3 - + 3 analog input leakage cur- rent i ain ann [2] 3.0v v dd 5.5v t a =25 c - 1 - + 1 ma 3.0v v dd 5.5v t a =125 c - 3 - + 3 ma pull-up resistance r up pnn_m [3] initx 3.0v v dd 3.6v 40 100 160 kw 4.5v v dd 5.5v 25 50 100 pull-down resistance r down pnn_m [4] 3.0v v dd 3.6v 40 100 180 kw 4.5v v dd 5.5v 25 50 100 input capacitance c in all except v dd 5, v dd 5r, v ss 5, av cc 5, av ss 5, avrh5 f = 1 mhz - 5 15 pf ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
mb91460b series document number: 002-04608 rev. *a page 103 of 126 power supply current f467ba f466ba i cc v dd 5r clkb: 96 mhz clkp: 48 mhz clkt: 48 mhz clkcan: 48 mhz ? 120 150 ma code fetch from flash i cch v dd 5r t a ? ? 25 ? c ? 30 150 ? a at stop mode [5] t a ? ? 105 ? c ? 0.4 2.0 ma t a ? ? 125 ? c ? 1.0 5.0 ma t a ? ? 25 ? c ? 100 500 ? a rtc: 4 mhz mode [5] t a ? ? 105 ? c ? 0.5 2.4 ma t a ? ? 125 ? c ? 1.1 5.4 ma t a ? ? 25 ? c ? 50 250 ? a rtc: 100 khz mode [5] t a ? ? 105 ? c ? 0.45 2.2 ma t a ? ? 125 ? c ? 1.05 5.2 ma i lve v dd 5 ?? 70 150 ? a external low voltage detection i lvi v dd 5r ?? 50 100 ? a internal low voltage detection i osc v dd 5 ?? 250 500 ? a main clock (4 mhz) ?? 20 40 ? a sub clock (32 khz) power supply current f465bb f464bb i cc v dd 5r clkb: 100 mhz clkp: 50 mhz clkt: 50 mhz clkcan: 50 mhz - 110 140 ma code fetch from flash i cch v dd 5r t a ? ? 25 ? c - 30 150 ? a at stop mode [5] t a ? ? 105 ? c-0.32.0ma t a ? ? 125 ? c - 0.75 5.0 ma t a ? ? 25 ? c - 100 500 ? a rtc: 4 mhz mode [5] t a ? ? 105 ? c-0.52.4ma t a ? ? 125 ? c - 0.85 5.4 ma t a ? ? 25 ? c - 50 250 ? a rtc: 100 khz mode [5] t a ? ? 105 ? c-0.42.2ma t a ? ? 125 ? c-0.85.2ma i lve v dd 5 ?? 70 150 ? a external low voltage detection i lvi v dd 5r ?? 50 100 ? a internal low voltage detection i osc v dd 5 - - 250 500 ? a main clock (4 mhz) - - 20 40 ? a sub clock (32 khz) 1. pnn_m includes all gpio pins . analog (an) channels and pullup/pulldown are disabled. 2. ann includes all pins where an channels are enabled. 3. pnn_m includes all gpio pins. the pull up resistors must be e nabled by pper/ppcr setting and the pins must be in input direct ion. 4. pnn_m includes all gpio pins. the pull down resistors must be enabled by pper/ppcr setting and the pins must be in input dire ction. 5. main regulator off, sub regulator se t to 1.2v, low voltage detection disabled. parameter symbol pin name condition value unit remarks min typ max
mb91460b series document number: 002-04608 rev. *a page 104 of 126 15.4 a/d converter characteristics (v dd 5 ? av cc 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) note: the accuracy gets worse as avrh - avrl becomes smaller parameter symbol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? 3 ? ? 3lsb nonlinearity error ?? ? 2.5 ? ? 2.5 lsb differential nonlinearity error ?? ? 1.9 ? ? 1.9 lsb zero reading voltage v ot ann avrl ? 1.5 lsb avrl ? 0.5 lsb avrl ? 2.5 lsb v full scale reading voltage v fst ann avrh ? 3.5 lsb avrh ? 1.5 lsb avrh ? 0.5 lsb v compare time t comp ? 0.6 ? 16,500 ? s 4.5 v av cc 5 5.5 v 2.0 ??? s 3.0 v av cc 5 4.5 v sampling time t samp ? 0.4 ??? s 4.5 v av cc 5 5.5 v, r ext < 2 k ? 1.0 ??? s 3.0 v av cc 5 4.5 v, r ext < 1 k ? conversion time t conv ? 1.0 ??? s 4.5 v av cc 5 5.5 v 3.0 ??? s 3.0 v av cc 5 4.5 v input capacitance c in ann ?? 11 pf input resistance r in ann ?? 2.6 k ? 4.5 v av cc 5 5.5 v ?? 12.1 k ? 3.0 v av cc 5 4.5 v analog input leakage current i ain ann ? 1 ? ? 1 ? at a ? ? 25 ? c ? 3 ? ? 3 ? at a ? ? 125 ? c analog input voltage range v ain ann avrl ? avrh v offset between input channels ? ann ?? 4lsb
mb91460b series document number: 002-04608 rev. *a page 105 of 126 1. supply current at av cc 5, if a/d converter and alarm comparator are not operating, (v dd 5 = av cc 5 = avrh = 5.0 v) 2. input current at avrh5, if a/d converter is not operating, (v dd 5 = av cc 5 = avrh = 5.0 v) 3. the current consumption per adc macro is given here. on devices having more then one a/d converter, the current values have to be multiplied by the number of macros. sampling time calculation t samp = ( 2.6 kohm + r ext ) 11pf 7; for 4.5v av cc 5 5.5v t samp = (12.1 kohm + r ext ) 11pf 7; for 3.0v av cc 5 4.5v conversion time calculation t conv = t samp + t comp 15.4.1 definition of a/d converter terms resolution analog variation that is recognizable by the a/d converter. nonlinearity error deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000 b ? 00 0000 0001 b ) and the full scale transition point (11 1111 1110 b ? 11 1111 1111 b ). differential nonlinearity error deviation of the input voltage from the ideal value that is required to change the output code by 1 lsb. total error this error indicates the difference between actual and theoretical values, including the zero transition erro r, full scale tra nsition error, and nonlinearity error. parameter symbol pin name value unit remarks min typ max reference voltage range avrh avrh5 0.75 av cc 5- av cc 5v avrl av ss 5av ss 5-av cc 5 0.25 v power supply current per adc macro [3] i a av cc 5 - 2.5 5 ma a/d converter active i ah av cc 5- - 5 a a/d converter not operated [1] reference voltage current per adc macro [3] i r avrh5 - 0.7 1 ma a/d converter active i rh avrh5 - - 5 a a/d converter not operated [2]
mb91460b series document number: 002-04608 rev. *a page 106 of 126 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss 5 avrh 0.5 lsb' {1 lsb? (n - 1) + 0.5 lsb?} 1.5 lsb? analog input total error digital output actual conversion characteristics v nt ( measurement value) ideal characteristics actual conversion characteristics total error of digital output n ? 1 lsb' v nt - {1 lsb' (n - 1) + 0.5 lsb'} n: a/d converter digital output value v ot ' (ideal value) ? av ss 5 ? 0.5 lsb' [v] v fst ' (ideal value) ? avrh ? 1.5 lsb' [v] v nt : voltage at which the digita l output changes from (n ? 1) h to n h 1lsb' (ideal value) ? 1024 avrh ? av ss 5 [v]
mb91460b series document number: 002-04608 rev. *a page 107 of 126 (n+1) h n h (n-1) h (n-2) h av ss 5 avrh 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss 5 avrh {1 lsb (n - 1) + v ot } analog input analog input differential nonlinearity error nonlinearity error digital output digital output actual conversion characteristics v fst (measurement value) v nt (measurement value) actual conversion characteristics ideal characteristics v to (measurement value) actual conversion characteristics v nt (measurement value) v fst (measurement value) nonlinearity error of digital output n ? 1lsb v nt ? {1lsb (n ? 1) ? v ot } [lsb] differential nonlinearity error of digital output n ? 1lsb v ( n ? 1 ) t ? v nt ? 1 [lsb] 1lsb ? 1022 v fst ? v ot [v] n: a/d converter digital output value v ot: voltage at which the digital output changes from 000 h to 001 h . v fst: voltage at which the digita l output changes from 3fe h to 3ff h . actual conversion characteristics ideal characteristics
mb91460b series document number: 002-04608 rev. *a page 108 of 126 15.5 alarm comparator characteristics 1. the fast alarm comparator mode is enabled by se tting acsr.md=1 setting acsr.md=0 sets the normal mode. parameter symbol pin name value unit remarks min typ max power supply current i a5almf av cc 5 ? 25 40 ? a alarm comparator en- abled in fast mode (per channel) [1] i a5alms ? 710 ? a alarm comparator en- abled in normal mode (per channel) [1] i a5almh ?? 5 ? a alarm comparator dis- abled alarm pin input current i alin alarm_n ? 1 ? ? 1 ? at a =25 ? c ? 3 ? ? 3 ? at a =125 ? c alarm pin input voltage range v alin 0 ? av cc 5v alarm upper limit voltage v iah av cc 5 0.78 - 3% av cc 5 0.78 av cc 5 0.78 + 3% v alarm lower limit voltage v ial av cc 5 0.36 - 5% av cc 5 0.36 av cc 5 0.36 + 5% v alarm hysteresis voltage v iahys 50 - 250 mv alarm input resistance r in 5 ?? m ? comparion time t compf ? 0.1 0.2 ? s alarm comparator enabled in fast mode [1] t comps ? 12 ? s alarm comparator enabled in normal mode [1]
mb91460b series document number: 002-04608 rev. *a page 109 of 126 15.6 flash memory program/erase characteristics 15.6.1 mb91f467ba/466ba (v dd 5 ? 3.0 v to 5.5 v, v dd 5r ? 3.0 v to 5.5 v, v ss 5 ? 0 v, t a ? ? 40 ? c to ? 105 ? c) 1. this value was converted from the results of evaluating the reliability of the te chnology (using arrhenius equation to conve rt high temperature measurements into normalized value at 85 o c) 15.6.2 mb91f465bb/464bb (v dd 5 ? 3.0 v to 5.5 v, v dd 5r ? 3.0 v to 5.5 v, v ss 5 ? 0 v, t a ? ? 40 ? c to ? 105 ? c) 1. this value was converted from the resu lts of evaluating the reliability of the technology (using arrhenius equation to conve rt high temperature mea- surements into normalized value at 85 o c) parameter value unit remarks min typ max sector erase time - 0.5 2.0 s erasure programming time not included chip erase time - n*0.5 n*2.0 s n is the number of flash sector of the device word (16-bit width) program- ming time - 6 100 ? s system overhead time not included program/erase cycle 10 000 cycle flash data retention time 20 year [1] parameter value unit remarks min typ max sector erase time - 0.9 3.6 s erasure programming time not included chip erase time - n*0.9 n*3.6 s n is the number of flash sector of the device word (16-bit or 32-bit width) programming time - 23 370 ? s system overhead time not included program/erase cycle 10 000 cycle flash data retention time 20 year [1]
mb91460b series document number: 002-04608 rev. *a page 110 of 126 15.7 ac characteristics 15.7.1 clock timing (v dd 5 ? 3.0 v to 5.5 v, vss5 ? avss5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) figure 3. clock timing condition 15.7.2 reset input ratings (v dd 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) parameter symbol pin name value unit condition min typ max clock frequency f c x0 x1 3.5 4 16 mhz opposite phase external supply or crystal x0a x1a 32 32.768 100 khz parameter symbol pin name condition value unit min max initx input time (at power-on) t intl initx ? 8 ? ms initx input time (other than the above) 20 ?? s 0.8 v cc 0.2 v cc p wh p wl t c x0, x1, x0a, x1a 0.2 v cc t intl initx
mb91460b series document number: 002-04608 rev. *a page 111 of 126 15.7.3 lin-usart timings at v dd 5 = 3.0 to 5.5 v conditions during ac measurements all ac tests were measured under the following conditions: ? - io drive = 5 ma ? - v dd 5 = 3.0 v to 5.5 v, i load = 3 ma ? - v ss 5 = 0 v ? - t a = -40 ? c to +125 ? c ? - c l = 50 pf (load capacity value of pins when testing) ? - vol = 0.2 x v dd 5 ? - voh = 0.8 x v dd 5 ? - epilr = 0, pilr = 1 (automotive level = worst case) (v dd 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) 1. parameter m depends on t scyci and can be calculated as : if t scyci ? 2*k*t clkp , then m ? k, where k is an integer > 2 if t scyci ? (2*k ? 1)*t clkp , then m ? k ? 1, where k is an integer > 1 notes : the above values are ac characteristics for clk synchronous mode. t clkp is the cycle time of the peripheral clock. parameter symbol pin name condition v dd 5 ? 3.0 v to 4.5 v v dd 5 ? 4.5 v to 5.5 v unit min max min max serial clock cycle time t scyci sckn internal clock operation (master mode) 4 t clkp -4 t clkp -ns sck sot delay time t slovi sckn sotn - 30 30 - 20 20 ns sot sck delay time t ovshi sckn sotn m t clkp - 30 [1] -m t clkp - 20 [1] -ns valid sin sck setup time t ivshi sckn sinn t clkp + 55 - t clkp + 45 - ns sck valid sin hold time t shixi sckn sinn 0-0-ns serial clock ?h? pulse width t shsle sckn external clock operation (slave mode) t clkp + 10 - t clkp + 10 - ns serial clock?l? pulse width t slshe sckn t clkp + 10 - t clkp + 10 - ns sck sot delay time t slove sckn sotn -2 t clkp + 55 - 2 t clkp + 45 ns valid sin sck setup time t ivshe sckn sinn 10 - 10 - ns sck valid sin hold time t shixe sckn sinn t clkp + 10 - t clkp + 10 - ns sck rising time t fe sckn - 20 - 20 ns sck falling time t re sckn - 20 - 20 ns
mb91460b series document number: 002-04608 rev. *a page 112 of 126 figure 4. internal clock mode (master mode) figure 5. external clock mode (slave mode) t ivshi v oh t shixi t slovi t scyci v ol sotn sckn for escr:sces = 0 sckn for escr:sces = 1 t ovshi v ol v ol v ol v ol v ol v oh v oh v oh v oh v oh sinn t ivshe v oh t shixe t slove t slshe v ol sotn sckn for escr:sces = 0 sckn for escr:sces = 1 v ol v ol v ol v ol v oh v oh v oh v ol v oh v oh v oh sinn t shsle v ol t re v oh t fe v ol
mb91460b series document number: 002-04608 rev. *a page 113 of 126 15.7.4 i 2 c ac timings at v dd 5 = 3.0 to 5.5 v conditions during ac measurements all ac tests were measured under the following conditions: ? -io drive = 3 ma ? -v dd 5 = 3.0 v to 5.5 v, i load = 3 ma ? -v ss 5 = 0 v ? -ta = - 40 c to + 125 c ? -c l = 50 pf ? -vol = 0.3 v dd 5 ? -voh = 0.7 v dd 5 ? -epilr = 0, pilr = 0 (cmos hysteresis 0.3 v dd 5/0.7 v dd 5) 15.7.4.1 fast mode: (v dd 5 ? 3.5 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) 1. the noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, de pending on the phase relationship between i 2 c signals (sda, scl) and peripheral clock. note: t clkp is the cycle time of the peripheral clock. parameter symbol pin name value unit remark min max scl clock frequency f scl scln 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is gen- erated t hd;sta scln, sdan 0.6 ?? s low period of the scl clock t low scln 1.3 ?? s high period of the scl clock t high scln 0.6 ?? s setup time for a repeated start condition t su;sta scln, sdan 0.6 ?? s data hold time for i 2 c-bus devices t hd;dat scln, sdan 0 0.9 ? s data setup time t su;dat scln sdan 100 ? ns rise time of both sda and scl signals t r scln, sdan 20 + 0.1cb 300 ns fall time of both sda and scl signals t f scln, sdan 20 + 0.1cb 300 ns setup time for stop condition t su;sto scln, sdan 0.6 ?? s bus free time between a stop and start condition t buf scln, sdan 1.3 ?? s capacitive load for each bus line c b scln, sdan ? 400 pf pulse width of spike suppressed by input filter t sp scln, sdan 0 (1..1.5) t clkp ns [1]
mb91460b series document number: 002-04608 rev. *a page 114 of 126 sda s sr p s scl t hd;sta tr tr t sp t su;st0 t su;sta t su;dat t hd;dat t hd;sta t low t high t buf tf tf
mb91460b series document number: 002-04608 rev. *a page 115 of 126 15.7.5 free-run timer clock (v dd 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) note : t clkp is the cycle time of the peripheral clock. 15.7.6 trigger input timing (v dd 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) note: t clkp is the cycle time of the peripheral clock. parameter symbol pin name condition value unit min max input pulse width t tiwh t tiwl ckn ? 4t clkp ? ns parameter symbol pin name condition value unit min max input capture input trigger t inp icun ? 5t clkp ? ns a/d converter trigger t atgx atgx ? 5t clkp ? ns t tiwh t tiwl ckn v ih v ih v il v il icun, atgx t atgx, t inp
mb91460b series document number: 002-04608 rev. *a page 116 of 126 15.7.7 external bus ac timings at v dd 35 ? 3.0 to 5.5 v note: this chapter is applicable to mb91f467ba/f466ba conditions during ac measurements all ac tests were measured under the following conditions: ? -io drive ? 5 ma ? -v dd 35 ? 4.5 v to 5.5 v, i load ? 3 ma ? -v ss 5 ? 0 v ? -ta ? ? 40 ? c to ? 125 ? c ? -c l ? 50 pf ? -vol ? 0.5 v dd 35 ? -voh = 0.5 v dd 35 ? -epilr ? 0, pilr ? 1 (automotive level ? worst case) 15.7.7.1 basic timing (v dd 35 ? 3.0 v to 5.5 v, vss5 ? avss5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) note: t clkt is the cycle time of the external bus clock. parameter symbol pin name value unit min max sysclk t clch sysclk 1/2 x t clkt - 1 1/2 t clkt + 9 ns t chcl 1/2 t clkt - 9 1/2 t clkt + 1 ns sysclk to csxn delay time t clcsl sysclk csxn -8ns t clcsh -12ns sysclk to csxn delay time (addr cs delay) t chcsl - 6 + 1 ns sysclk to address valid delay time t clav sysclk a21 to a0 -13ns
mb91460b series document number: 002-04608 rev. *a page 117 of 126 delayed csxn asx address baax t chcsl t clasl t clav t clbal t clash t clbah
mb91460b series document number: 002-04608 rev. *a page 118 of 126 15.7.7.2 synchronous/asynchronous read access (v dd 35 ? 3.0 v to 5.5 v, vss5 ? avss5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) parameter symbol pin name value unit min max sysclk to rdx delay time tchrl sysclk rdx - 7 1 ns tchrh - 4 2 ns data valid to rdx setup time tdsrh rdx d31 to d16 33 - ns rdx to data valid hold time trhdx rdx d31 to d16 0-ns sysclk to wrxn (as byte enable) delay time tclwrl sysclk wrxn -8ns tclwrh 0 - ns sysclk to csxn delay time tclcsl sysclk csxn -8ns tclcsh - 12 ns sysclk csxn wrxn (as byte enable) rdx data in t dsrh t rhdx t chrh t chrl t clwrl t clwrh t clcsh t clcsl
mb91460b series document number: 002-04608 rev. *a page 119 of 126 15.7.7.3 synchronous write access (v dd 35 ? 3.0 v to 5.5 v, vss5 ? avss5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) parameter symbol pin name value unit min max sysclk to wrxn delay time tclwrl sysclk wrxn -8ns tclwrh 0 - ns data valid to wrxn setup time tdswrl wrxn d31 to d16 - 7 - ns wrxn to data valid hold time twrhdh wrxn d31 to d16 t clkt - 20 - ns sysclk to csxn delay time tclcsl sysclk csxn -8ns tclcsh - 12 ns sysclk csxn wrxn data out t clwrh t clwrl t dswrl t wrhdh t clcsh t clcsl
mb91460b series document number: 002-04608 rev. *a page 120 of 126 15.7.7.4 asynchronous write access ( v dd 35 ? 3.0 v to 5.5 v , vss5 ? avss5 ? 0 v , t a ? ? 40 ? c to ? 125 ? c) parameter symbol pin name value unit min max wrxn to wrxn pulse width twrlwrh wrxn t clkt -ns data valid to wrxn setup time tdswrl wrxn d31 to d16 1/2 t clkt - 10 - ns wrxn to data valid hold time twrhdh wrxn d31 to d16 1/2 t clkt - 19 - ns wrxn to csxn delay time tclwrl wrxn csxn - 1/2 t clkt ns twrhch 1/2 t clkt -ns csxn wrxn data out twrhdh twrhch tclwrl twrlwrh tdswrl
mb91460b series document number: 002-04608 rev. *a page 121 of 126 15.7.7.5 rdy waitcycle insertion (v dd 35 ? 3.0 v to 5.5 v, vss5 ? avss5 ? 0 v, t a ? ? 40 ? c to ? 125 ? c) parameter symbol pin name value unit min max rdy setup time trdys sysclk rdy 34 ? ns rdy hold time trdyh sysclk rdy 0 ? ns sysclk rdy t rdys t rdyh
mb91460b series document number: 002-04608 rev. *a page 122 of 126 16. ordering information part number package remarks MB91F465BBPMC-GSE2 mb91f467bapmc-gse2 144-pin plastic lqfp (fpt-144p-m08) lead-free package
mb91460b series document number: 002-04608 rev. *a page 123 of 126 17. package dimension 144-pin pla s tic lqfp lead pitch 0.50 mm package width package length 20.0 20.0 mm lead s hape g u llwing sealing method pla s tic mold mo u nting height 1.70 mm max weight 1.20g code (reference) p-lfqfp144-20 20-0.50 144-pin pla s tic lqfp (fpt-144p-m08) (fpt-144p-m08) c 2003 fujitsu limited f144019s-c-4-6 detail s of "a" part 0.25(.010) (stand off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.008) 0.500.20 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ? ~8 ? 0.50(.020) "a" 0.08(.003) 0.1450.055 (.006.002) lead no. 1 36 index 37 72 73 108 109 144 0.220.05 (.009.002) m 0.08(.003) 20.000.10(.787.004)sq 22.000.20(.866.008)sq (mo u nting height) * dimen s ion s in mm (inche s ). note: the val u e s in parenthe s e s are reference val u e s . ?2003-2008 fujitsu microelectronics limited f144019s-c-4-7 note 1) * :val u e s do not incl u de re s in protr us ion. re s in protr us ion i s +0.25(.010)max(each s ide). note 2) pin s width and pin s thickne ss incl u de plating thickne ss . note 3) pin s width do not incl u de tie bar c u tting remainder.
mb91460b series document number: 002-04608 rev. *a page 124 of 126 18. revision history spansion publication number: ds07-16609-1e 19. main changes in this edition note: please see ?document history? for later revised information. version date remark 2.0 2008-06-19 initial version 2.1 2008-08-15 proof reading results from fj incorporated; corrected pinout drawings; io circuit types: corrected some typos like on the other datasheets; handling devices: updated the section "notes on ps register" for better understanding; interrupt vector table: corrected the footnotes flash: added note about the operation mode switchi ng capability in boot rom; corrected flash security vector fsv2 assignments, corrected section about parallel programming, corrected section pin connections in parallel programming mode so that there is only one page added section "poweron sequence in parallel programming mode"; electrical characteristics: removed the note that analog input/output pins cannot ac- cept +b signal input; splitted i lv into external and internal lv detection current adc characteristics: corrected the items about nonlinearity error; corrected the company name 3.0 2009-01-09 page 1: corrected document name field in top header block diagram: removed sck0 (lin-usart0 is asynchronous only) added ta=125c characteristics page section change results 104 15. electrical characteristics 15.4. a/d converter characteristics corrected the column ?value? and ?unit? of the parameter ?zero reading voltage? and ?full scale reading voltage?. (value : avrl - 1.5 avrl - 1.5 lsb avrl + 0.5 avrl + 0.5 lsb avrl + 2.5 avrl + 2.5 lsb avrh - 3.5 avrh - 3.5 lsb avrh - 1.5 avrh - 1.5 lsb avrh + 0.5 avrh + 0.5 lsb unit : lsb v )
mb91460b series document number: 002-04608 rev. *a page 125 of 126 document history document title: mb91f467ba/466ba, mb91f465bb/464bb, fr60 mb91460b series, 32-bit microcontroller datasheet document number: 002-04608 revision ecn orig. of change submission date description of change ** ? akih 08/17/2009 migrated to cypress and assigned document number 002-04608. no change to document contents or format. *a 5221423 akih 04/25/2016 updated to cypress template
document number: 002-04608 rev. *a revised april 25, 2016 page 126 of 126 mb91460b series ? cypress semiconductor corporation 2009-2016. this document is the property of cypress semiconductor corporation and its subsi diaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non-exclusive, nontransferable license (without the r ight to sublicense) (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units. cypress also gran ts you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any oth er use, reproduction, modification, translation, or compilation of the software is prohibited. cypress makes no warranty of any kind, express or implied, with regard to this document or any software, including, but not lim ited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of an y product or circuit described in this document. any informati on provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly d esign, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as crit ical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support de vices or systems, other medical devices or systems (including r esuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or syste m, or to affect its safety or effectiv eness. cypress is not liable, in whole or in part, and company shall and hereby does release cypress from any claim, damage, or other liability arising from or relate d to all unintended uses of cypress products. company shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inj ury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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